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Publication search results
found 157 matches
- 2003
- Aseem Agarwal, Vladimir Zolotov, David T. Blaauw:
Statistical timing analysis using bounds and selective enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1243-1260 (2003) - Zaid Al-Ars, Ad J. van de Goor:
Test generation and optimization for DRAM cell defects using electrical simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1371-1384 (2003) - Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
On the skew-bounded minimum-buffer routing tree problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 937-945 (2003) - Cesare Alippi, Andrea Galbusera, Marco Stellini:
An application-level synthesis methodology for multidimensional embedded processing systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1457-1470 (2003) - Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Solving difficult instances of Boolean satisfiability in the presence of symmetry. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1117-1137 (2003) - Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah:
Satometer: how much have we searched? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 995-1004 (2003) - Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A practical methodology for early buffer and wire resource allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 573-583 (2003) - Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 241-253 (2003) - Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
Effective free space management for cut-based placement via analytical constraint generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1343-1353 (2003) - Charles J. Alpert, Sachin S. Sapatnekar:
Guest editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 385-386 (2003) - M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Fault equivalence identification in combinational circuits using implication and evaluation techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 922-936 (2003) - Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna:
Design automation with mixtures of proof strategies for propositional logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1042-1048 (2003) - Mohab Anis, Shawki Areibi, Mohamed I. Elmasry:
Design and optimization of multithreshold CMOS (MTCMOS) circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1324-1342 (2003) - Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj:
Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 337-345 (2003) - Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Three-level logic minimization based on function regularities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1005-1016 (2003) - Thomas Binder, Andreas Hössinger, Siegfried Selberherr:
Rigorous integration of semiconductor process and device simulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1204-1214 (2003) - David M. Binkley, C. E. Hopper, Steve D. Tucker, Brian C. Moss, James M. Rochelle, Daniel Foty:
A CAD methodology for optimizing transistor current and sizing in analog CMOS design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(2): 225-237 (2003) - David T. Blaauw, Luciano Lavagno:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 962-963 (2003) - David T. Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta:
Static electromigration analysis for on-chip signal interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 39-48 (2003) - Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh:
Creating and exploiting flexibility in rectilinear Steiner trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 605-615 (2003) - Ulrich Brenner, André Rohe:
An effective congestion-driven placement framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 387-394 (2003) - Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hierarchical whitespace allocation in top-down placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1550-1556 (2003) - Giorgio Casinovi, Chad Young:
Estimation of power dissipation in switched-capacitor circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12): 1625-1636 (2003) - Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria:
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 346-351 (2003) - Anshuman Chandra, Krishnendu Chakrabarty:
A unified approach to reduce SOC test data volume, scan power and testing time. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 352-363 (2003) - Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan:
Multilevel global placement with congestion control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 395-409 (2003) - Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska:
A new reasoning scheme for efficient redundancy addition and removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 945-951 (2003) - Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang:
Performance-driven mapping for CPLD architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1424-1431 (2003) - Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen:
INDUCTWISE: inductance-wise interconnect simulator and extractor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 884-894 (2003) - Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee:
Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 363-370 (2003)
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