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Publication search results
found 29 matches
- 1994
- S. K. Nandy:
Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment. VLSI Design 1(2): 155-167 (1994) - S. K. Nandy, R. B. Panwar:
Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors. VLSI Design 1(2): 127-154 (1994) - Michael J. Batek, John P. Hayes:
Optimal Testing and Design of Adders. VLSI Design 1(4): 285-298 (1994) - Inderpreet Bhasin, Joseph G. Tront:
Block-Level Logic Extraction from CMOS VLSI Layouts. VLSI Design 1(3): 243-259 (1994) - Fadi Busaba, Parag K. Lala:
An Approach for Self-Checking Realization of Interacting Finite State Machines. VLSI Design 1(4): 335-343 (1994) - Chien-In Henry Chen:
Using PDM on Multiport Memory Allocation in Data Path. VLSI Design 1(3): 217-232 (1994) - Chien-In Henry Chen, Gerald E. Sobelman:
Cluster Partitioning Techniques for Data Path Synthesis. VLSI Design 1(3): 181-192 (1994) - Warren H. Debany Jr., Mark Gorniak, Anthony R. Macera, Daniel Daskiewich, Kevin A. Kwiat, Heather B. Dussault:
Empirical Bounds on Fault Coverage Loss Due to LFSR Aliasing. VLSI Design 1(4): 313-326 (1994) - Michael Ogbonna Esonu, Dhamin Al-Khalili, Côme Rozon:
Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits. VLSI Design 1(4): 261-276 (1994) - Marwan A. Jabri:
Building Rectangular Floorplans-A Graph Theoretical Approach. VLSI Design 1(2): 99-111 (1994) - Kevin T. Kornegay, Robert W. Brodersen:
Integrated Test Solutions for a System Design Environment. VLSI Design 1(4): 345-357 (1994) - Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong, Sankaran M. Menon:
Resolution Enhancement in IDDQ Testing for Large ICs. VLSI Design 1(4): 277-284 (1994) - Ben Mathew, Daniel G. Saab:
Partial Reset: An Alternative DFT Approach. VLSI Design 1(4): 299-311 (1994) - Rochit Rajsuman:
Special Issue on Digital Hardware Testing. VLSI Design 1(4): i (1994) - Rochit Rajsuman, Kamal Rajkanan:
STD Architecture: A Practical Approach to Test M-Bits Random Access Memories. VLSI Design 1(4): 327-334 (1994) - Sajjan G. Shiva, Judit U. Jones:
A VHDL Based Expert System for Hardware Synthesis. VLSI Design 1(2): 113-126 (1994) - Xiaoyu Song:
An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model. VLSI Design 1(3): 233-242 (1994) - Krishnamurthy Subramanian, Mehdi R. Zargham:
Distributed and Parallel Demand Driven Logic Simulation Algorithms. VLSI Design 1(2): 169-179 (1994) - San-Yuan Wu, Sartaj Sahni:
Fast Algorithms to Partition Simple Rectilinear Polygons. VLSI Design 1(3): 193-215 (1994) - 1993
- Michael J. Bryan, Srinivas Devadas, Kurt Keutzer:
Analysis and Design of Regular Structures for Robust Dynamic Fault Testability. VLSI Design 1(1): 45-60 (1993) - Sunil R. Das:
Guest Editorial. VLSI Design 1(1): iii-iv (1993) - Warren H. Debany Jr.:
Coverage of Node Shorts Using Internal Access and Equivalence Classes. VLSI Design 1(1): 71-85 (1993) - Samiha Mourad:
Computer-Aided Testing Systems: Evaluation and Benchmark Circuits. VLSI Design 1(1): 87-97 (1993) - Walid A. Najjar, Pradip K. Srimani:
Conditional Disconnection Probability in Star Graphs. VLSI Design 1(1): 61-70 (1993) - Jacob Savir, Paul H. Bardell:
Built-In Self-Test: Milestones and Challenges. VLSI Design 1(1): 23-44 (1993) - Rajiv Sharma, Kewal K. Saluja:
Theory, Analysis and Implementation of an On-Line BIST Technique. VLSI Design 1(1): 9-22 (1993) - Earl E. Swartzlander Jr., Miroslaw Malek:
Overlapped Subarray Segmentation: An Efficient Test Method for Cellular Arrays. VLSI Design 1(1): 1-7 (1993) - Editorial. VLSI Design 1(1): i-ii (1993)
- About the Editor in Chief and the Guest Editor. VLSI Design 1(1): v (1993)
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retrieved on 2024-08-08 22:37 CEST from data curated by the dblp team
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