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Publication search results
found 121 matches
- 1990
- Magdy S. Abadir, Jack Ferguson:
An improved layout verification algorithm (LAVA). EURO-DAC 1990: 391-395 - Vishwani D. Agrawal, Kwang-Ting Cheng:
An architecture for synthesis of testable finite state machines. EURO-DAC 1990: 612-616 - Mart Altmäe:
MINT: a VHDL simulation system. EURO-DAC 1990: 102-106 - Grazia Arato, Giuseppe Bussolino, Anna M. Fiammengo, Roberto Manione:
ACCORDO: second generation floor planning. EURO-DAC 1990: 266-270 - Maria J. Avedillo, José M. Quintana, José Luis Huertas:
A new method for the state reduction of incompletely specified finite sequential machines. EURO-DAC 1990: 552-556 - Bernd Becker, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor, Hans-Georg Osthof, Gisela Pitsch, Uwe Sparmann:
A graphical system for hierarchical specifications and checkups of VLSI circuits. EURO-DAC 1990: 174-179 - Daniel K. Beece, Robert F. Damiano, Georgina Papp, R. Schoen:
The EVE companion simulator. EURO-DAC 1990: 290-295 - Michel R. C. M. Berkelaar, Jochen A. G. Jess:
Gate sizing in MOS digital circuits with linear programming. EURO-DAC 1990: 217-221 - Neerav Berry, Barry M. Pangrle:
SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system. EURO-DAC 1990: 78-82 - David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham:
Derivation of signal flow for switch-level simulation. EURO-DAC 1990: 301-305 - Philippe Bondono, Ahmed Amine Jerraya, Armand Hornik, Bernard Courtois, D. Bonifas:
NAUTILE: a safe environment for silicon compilation. EURO-DAC 1990: 605-609 - Eric William Burger, Guido Dedene:
Economics of point accelleration. EURO-DAC 1990: 424-428 - R. Burgess, C. Wouters:
PARAGON: a new package for gate matrix layout synthesis. EURO-DAC 1990: 129-134 - D. F. Burrows:
The use of computer-aided software engineering technology in systems and software design. EURO-DAC 1990: 434-438 - Yang Cai, D. F. Wong:
Optimal via-shifting in channel compaction. EURO-DAC 1990: 186-190 - Raul Camposano, Reinaldo A. Bergamaschi:
Redesign using state splitting. EURO-DAC 1990: 157-161 - Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda:
Diagnosis oriented test pattern generation. EURO-DAC 1990: 470-474 - Daniele D. Caviglia, Giacomo M. Bisio, Francesco Curatelli, L. Giovannacci, Luigi Raffo:
Pre-placement of VLSI blocks through learning neural networks. EURO-DAC 1990: 650-654 - Wu-Tung Cheng, Janak H. Patel:
PROOFS: a super fast fault simulator for sequential circuits. EURO-DAC 1990: 475-479 - Che W. Chiou, Ted C. Yang:
Fully testable PLA design with minimal extra input. EURO-DAC 1990: 633-638 - Hélène Collavizza:
Functional semantics of microprocessors at the microprogram level and correspondence with the machine instruction level. EURO-DAC 1990: 52-56 - Jason Cong, C. L. Liu:
On the k-layer planar subset and via minimization problems. EURO-DAC 1990: 459-463 - Robert A. Cottrell:
Event-driven behavioural simulation of analogue transfer functions. EURO-DAC 1990: 240-243 - Olivier Coudert, Christian Berthet, Jean Christophe Madre:
Formal boolean manipulations for the verification of sequential machines. EURO-DAC 1990: 57-61 - F. Darlay, Bernard Courtois:
Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks. EURO-DAC 1990: 344-349 - Rene David, S. Rahal, J. L. Rainard:
Some relationships between delay testing and stuck-open testing in CMOS circuits. EURO-DAC 1990: 339-343 - Antoine Delaruelle, O. McArdle, Jef L. van Meerbergen, Cees Niessen:
Synthesis of delay functions in DSP compilers. EURO-DAC 1990: 68-72 - Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne:
Path runner: an accurate and fast timing analyser. EURO-DAC 1990: 529-533 - Liliana Díaz-Olavarrieta, Safwat G. Zaky:
A new synthesis technique for multilevel combinational circuits. EURO-DAC 1990: 222-227 - Keith R. Dimond, Samir Hassan:
An incremental functional simulator implemented on a network of transputers. EURO-DAC 1990: 296-300
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