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Publication search results
found 75 matches
- 2004
- M. Ali-Bakhshian, K. Sadeghi:
A novel continuous-time common-mode feedback for low-voltage switched-OPAMP. ISLPED 2004: 296-300 - Hari Ananthan, Chris H. Kim, Kaushik Roy:
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. ISLPED 2004: 8-13 - Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii:
Post-layout leakage power minimization based on distributed sleep transistor insertion. ISLPED 2004: 138-143 - Amirali Baniasadi, Andreas Moshovos:
SEPAS: a highly accurate energy-efficient branch predictor. ISLPED 2004: 38-43 - Ray Bryant:
Why hot chips are no longer "cool". ISLPED 2004: 1 - Benton H. Calhoun, Anantha P. Chandrakasan:
Characterizing and modeling minimum energy operation for subthreshold circuits. ISLPED 2004: 90-95 - Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy:
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. ISLPED 2004: 248-251 - Deming Chen, Jason Cong:
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. ISLPED 2004: 70-73 - Youngjin Cho, Naehyuck Chang:
Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling. ISLPED 2004: 387-392 - Kihwan Choi, Ramakrishna Soma, Massoud Pedram:
Dynamic voltage and frequency scaling based on workload decomposition. ISLPED 2004: 174-179 - Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty:
Managing standby and active mode leakage power in deep sub-micron design. ISLPED 2004: 274-279 - John Cornish:
Balanced energy optimization. ISLPED 2004: 186 - Supriyo Datta:
Understanding nanoscale conductors. ISLPED 2004: 325 - Mohamed Elgebaly, Manoj Sachdev:
Efficient adaptive voltage scaling system through on-chip critical path emulation. ISLPED 2004: 375-380 - Maged Ghoneima, Yehea I. Ismail:
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. ISLPED 2004: 66-69 - Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou:
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes. ISLPED 2004: 381-386 - Stefano Gregori, Yunlei Li, Huijuan Li, Jin Liu, Franco Maloberti:
2.45 GHz power and data transmission for a low-power autonomous sensors platform. ISLPED 2004: 269-273 - Kim M. Hazelwood, David M. Brooks:
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization. ISLPED 2004: 326-331 - Seongmoo Heo, Krste Asanovic:
Power-optimal pipelining in deep submicron technology. ISLPED 2004: 218-223 - Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose:
Microarchitectural techniques for power gating of execution units. ISLPED 2004: 32-37 - Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu:
Architecting voltage islands in core-based system-on-a-chip designs. ISLPED 2004: 180-185 - Ming-Feng Huang, Shuenn-Yuh Lee, Chung J. Kuo:
A CMOS even harmonic mixer with current reuse for low power applications. ISLPED 2004: 290-295 - Hans M. Jacobson:
Improved clock-gating through transparent pipelining. ISLPED 2004: 26-31 - Ravindra Jejurikar, Rajesh K. Gupta:
Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems. ISLPED 2004: 78-81 - Himanshu Kaul, Dennis Sylvester, Mark A. Anders, Ram Krishnamurthy:
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. ISLPED 2004: 194-199 - Mohamed Kawokgy, C. André T. Salama:
Low-power asynchronous viterbi decoder for wireless applications. ISLPED 2004: 286-289 - Stefanos Kaxiras, Polychronis Xekalakis:
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors. ISLPED 2004: 108-113 - Vishal Khandelwal, Ankur Srivastava:
Active mode leakage reduction using fine-grained forward body biasing strategy. ISLPED 2004: 150-155 - Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang:
Nanoscale CMOS circuit leakage power reduction by double-gate device. ISLPED 2004: 102-107 - Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge:
Microarchitectural power modeling techniques for deep sub-micron microprocessors. ISLPED 2004: 212-217
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retrieved on 2024-05-18 18:49 CEST from data curated by the dblp team
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