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Publication search results
found 74 matches
- 2002
- Afshin Abdollahi, Farzan Fallah:
Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits. IWLS 2002: 419-424 - Anas Al-Rabadi:
Symmetry as a Base for a New Decomposition of Boolean Logic. IWLS 2002: 273-278 - Anas Al-Rabadi, Lee W. Casperson:
Optical Realizations of Reversible Logic. IWLS 2002: 21-26 - Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah:
ZBDD-Based Backtrack Search SAT Solver. IWLS 2002: 131-136 - Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
Efficient Gate and Input Ordering for Circuit-to-BDD Conversion. IWLS 2002: 137-142 - Tomas Bengtsson, Andrés Martinelli, Elena Dubrova:
A Fast Heuristic Algorithm for Disjunctive. IWLS 2002: 51-56 - Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Implicit Test of Regularity for Not Completely Specified Boolean Functions. IWLS 2002: 345-350 - Alexandre V. Bystrov, Alexandre Yakovlev:
Synthesis of Asynchronous Circuits with Predictable Latency. IWLS 2002: 239-243 - Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan:
An Efficient Two-Level Filter Scheme for Low Power Cache. IWLS 2002: 61-66 - Tiberiu Chelcea, Steven M. Nowick:
Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems. IWLS 2002: 355-360 - Silviu M. S. A. Chiricescu, Michael A. Schuette, Herman Schmit, Robin Glinton:
Synthesis of Morphable Multipliers. IWLS 2002: 109-113 - Geun Rae Cho, Tom Chen:
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS 2002: 289-294 - Jason Cong, Joey Y. Lin, Wangning Long:
Enhanced SPFD Rewiring on Improving Rewiring Ability. IWLS 2002: 91-96 - Jordi Cortadella:
Bi-Decomposition and Tree-Height Reduction for Timing Optimization. IWLS 2002: 233-238 - Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin:
Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS 2002: 191-196 - Stephen A. Edwards:
High-Level Synthesis from the Synchronous Language Esterel. IWLS 2002: 401-406 - Mohamed A. Elgamel, Magdy A. Bayoumi:
On Low Power High Level Synthesis Using Genetic Algorithms. IWLS 2002: 37-40 - Farzan Fallah:
Binary Time Frame Expansion. IWLS 2002: 314-319 - Petra Färm, Elena Dubrova:
Technology Mapping for Chemically Assembled Electronic Nanotechnology. IWLS 2002: 121-124 - S. G. Gibb, Laurence E. Turner:
The Automatic Generation of Application Specific Processors. IWLS 2002: 161-165 - Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera:
Experimental Study on Cell-Base High-Performance Datapath Design. IWLS 2002: 283-287 - Jie-Hong Roland Jiang, Robert K. Brayton:
On the Verification of Sequential Equivalence. IWLS 2002: 307-314 - Yunjian Jiang, Robert K. Brayton:
Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic. IWLS 2002: 327-332 - Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary. IWLS 2002: 339-344 - Chang Woo Kang, Massoud Pedram:
Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration. IWLS 2002: 295-300 - Pawel Kerntopf:
An Approach to Designing Complex Reversible Logic Gates. IWLS 2002: 31-36 - Pawel Kerntopf:
Nonlinear Sifting of Decision Diagrams. IWLS 2002: 85-90 - Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton:
Low Power Optimization Techniques for BDD Mapped Finite State Machines. IWLS 2002: 143-148 - Andrei B. Khlopotine, Marek A. Perkowski, Pawel Kerntopf:
Reversible Logic Synthesis by Iterative Compositions. IWLS 2002: 261-266 - Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS 2002: 103-108
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