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Publication search results
found 148 matches
- 1994
- Mark D. Aagaard, Miriam Leeser:
PBS: proven Boolean simplification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 459-470 (1994) - Arun Achyuthan, Mohamed I. Elmasry:
Mixed analog/digital hardware synthesis of artificial neural networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1073-1087 (1994) - Filip Van Aelten, Jonathan Allen, Srinivas Devadas:
Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 122-134 (1994) - Walter Allegretto, Bing Shen, P. Haswell, Zhongsheng Lai, Alexander M. Robinson:
Numerical modeling of a micromachined thermal conductivity gas pressure sensor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(10): 1247-1256 (1994) - Said Amellal, Bozena Kaminska:
Functional synthesis of digital systems with TASS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 537-552 (1994) - Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage:
Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 729-736 (1994) - Kurt Antreich, Helmut E. Graeb, Claudia U. Wieser:
Circuit analysis and optimization driven by worst-case distances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 57-71 (1994) - Y. Apanovich, Eugeny D. Lyumkis, Boris S. Polsky, Alex I. Shur, Peter A. Blakey:
Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 702-711 (1994) - Bechir Ayari, Bozena Kaminska:
A new dynamic test vector compaction for automatic test pattern generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 353-358 (1994) - Sina Balkir, Mehmet Yanilmaz, Martin A. Plonus:
Numerical integration using Bezier splines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 737-745 (1994) - S. Wayne Bollinger, Scott F. Midkiff:
Test generation for IDDQ testing of bridging faults in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(11): 1413-1418 (1994) - Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
An edge-based heuristic for Steiner routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1563-1568 (1994) - Daniel Brand, Vijay S. Iyengar:
Identification of redundant delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 553-565 (1994) - Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill:
Symbolic model checking for sequential circuit verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 401-424 (1994) - Yang Cai, Martin D. F. Wong:
On shifting blocks and terminals to minimize channel density. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 178-186 (1994) - Giorgio Casinovi, Jeen-Mo Yang:
Multi-level simulation of large analog systems containing behavioral models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(11): 1391-1399 (1994) - Víctor H. Champac, Antonio Rubio, Joan Figueras:
Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 359-369 (1994) - Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral K-way ratio-cut partitioning and clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1088-1096 (1994) - Ting-Hai Chao, Yu-Chin Hsu:
Rectilinear Steiner tree construction by local and global refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 303-309 (1994) - C. Y. Roger Chen, Cliff Yungchin Hou, Uminder Singh:
Optimal algorithms for bubble sort based non-Manhattan channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 603-609 (1994) - Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab:
Structural and behavioral synthesis for testability techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 777-785 (1994) - Beyin Chen, Chung-Len Lee:
A complement-based fast algorithm to generate universal test sets for multi-output functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 370-377 (1994) - Siu-Wing Cheng, Hsi-Chuan Chen, David Hung-Chang Du, Andrew Lim:
The role of long and short paths in circuit performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 857-864 (1994) - Charles C. Chiang, Chak-Kuen Wong, Majid Sarrafzadeh:
A weighted Steiner tree-based global router with simultaneous length and density minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1461-1469 (1994) - Vivek Chickermane, Jaushin Lee, Janak H. Patel:
Addressing design for testability at the architectural level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 920-934 (1994) - Tae Won Cho, Sam S. Pyo, J. Robert Heath:
PARALLEX: a parallel approach to switchbox routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 684-693 (1994) - Woo-Sung Choi, Jae-Gyung Ahn, Young-June Park, Hong-Shick Min, Chang-Gyu Hwang:
A time dependent hydrodynamic device simulator SNU-2D with new discretization scheme and algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 899-908 (1994) - Tai-Yu Chou, Zoltan J. Cendes:
Capacitance calculation of IC packages using the finite element method and planes of symmetry. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1159-1166 (1994) - Jason Cong, Yuzheng Ding:
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 1-12 (1994) - Henry Cox, Janusz Rajski:
On necessary and nonconflicting assignments in algorithmic test pattern generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 515-530 (1994)
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