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Joan Figueras
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2020 – today
- 2020
- [j46]Álvaro Gómez-Pau
, Emili Lupon, Luz Balado, Joan Figueras:
Indirect and adaptive test of analogue circuits based on preselected steady-state response measures. IET Circuits Devices Syst. 14(5): 611-618 (2020)
2010 – 2019
- 2019
- [j45]Rosa Rodríguez-Montañés
, Daniel Arumí
, Joan Figueras:
Postbond Test of Through-Silicon Vias With Resistive Open Defects. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2596-2607 (2019) - 2017
- [j44]Álvaro Gómez-Pau
, Luz Balado, Joan Figueras:
Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing. J. Electron. Test. 33(3): 315-328 (2017) - [c84]Elena Ioana Vatajelu
, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras:
Mitigating read & write errors in STT-MRAM memories under DVS. ETS 2017: 1-2 - 2016
- [j43]Álvaro Gómez-Pau
, Luz Balado, Joan Figueras:
Indirect test of M-S circuits using multiple specification band guarding. Integr. 55: 415-424 (2016) - [j42]Álvaro Gómez-Pau
, Luz Balado, Joan Figueras:
Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1386-1395 (2016) - [j41]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras:
Prebond Testing of Weak Defects in TSVs. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1503-1514 (2016) - [j40]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras:
Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1739-1748 (2016) - 2015
- [c83]Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras:
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. DATE 2015: 447-452 - [c82]Álvaro Gómez-Pau, Luz Balado, Joan Figueras:
Analog circuits testing using digitally coded indirect measurements. DTIS 2015: 1-6 - [c81]Elena I. Vatajelu
, Rosa Rodríguez-Montañés, Marco Indaco, Paolo Prinetto, Joan Figueras:
STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations. DTIS 2015: 1-6 - [c80]Elena I. Vatajelu
, Rosa Rodríguez-Montañés, Stefano Di Carlo
, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras:
Power-aware voltage tuning for STT-MRAM reliability. ETS 2015: 1-6 - 2014
- [j39]Víctor H. Champac, Hector Villacorta, Nestor Hernandez, Joan Figueras:
Skew violation verification in digital interconnect signals based on signal addition. IEICE Electron. Express 11(15): 20140201 (2014) - [j38]Elena I. Vatajelu, Álvaro Gómez-Pau
, Michel Renovell, Joan Figueras:
Sram cell stability metric under transient voltage noise. Microelectron. J. 45(10): 1348-1353 (2014) - [c79]Stefano Di Carlo
, Marco Indaco, Paolo Prinetto, Elena I. Vatajelu
, Rosa Rodríguez-Montañés, Joan Figueras:
Reliability estimation at block-level granularity of spin-transfer-torque MRAMs. DFT 2014: 75-80 - [c78]Álvaro Gómez-Pau, Luz Balado, Joan Figueras:
M-S specification binning based on digitally coded indirect measurements. ETS 2014: 1-6 - [c77]Rosa Rodríguez-Montañés, Daniel Arumí
, Joan Figueras:
Post-bond test of Through-Silicon Vias with open defects. ETS 2014: 1-6 - [c76]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras:
Pre-bond testing of weak defects in TSVs. IOLTS 2014: 31-36 - 2013
- [j37]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 301-312 (2013) - [c75]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras:
BIST architecture to detect defects in tsvs during pre-bond testing. ETS 2013: 1 - [c74]Álvaro Gómez-Pau, Luz Balado, Joan Figueras:
M-S test based on specification validation using octrees in the measure space. ETS 2013: 1-6 - 2012
- [c73]Elena I. Vatajelu, Joan Figueras:
Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation. DATE 2012: 1343-1348 - 2011
- [j36]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1911-1922 (2011) - [j35]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Gate Leakage Impact on Full Open Defects in Interconnect Lines. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2209-2220 (2011) - [c72]Elena I. Vatajelu
, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras:
Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric. Asian Test Symposium 2011: 413-418 - [c71]Elena I. Vatajelu, Joan Figueras:
Robustness analysis of 6T SRAMs in memory retention mode under PVT variations. DATE 2011: 980-985 - [c70]Elena Ioana Vatajelu
, Joan Figueras:
Statistical analysis of 6T SRAM data retention voltage under process variation. DDECS 2011: 365-370 - [c69]Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio González
, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanausú Ramírez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, Xingsheng Wang
, Paul Zuber:
New reliability mechanisms in memory design for sub-22nm technologies. IOLTS 2011: 111-114 - [c68]Madalin Neagu
, Liviu Miclea, Joan Figueras:
Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies. IOLTS 2011: 264-269 - 2010
- [j34]Víctor H. Champac, Victor Avendaño, Joan Figueras:
Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 256-269 (2010) - [c67]Alvaro Gómez, Ricard Sanahuja, Luz Balado, Joan Figueras:
Analog circuit test based on a digital signature. DATE 2010: 1641-1644 - [c66]Elena I. Vatajelu
, Georgios Panagopoulos, Kaushik Roy, Joan Figueras:
Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. ETS 2010: 69-74 - [c65]Rosa Rodríguez-Montañés, Daniel Arumí
, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Diagnosis of full open defects in interconnect lines with fan-out. ETS 2010: 233-238
2000 – 2009
- 2009
- [j33]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras:
Delay caused by resistive opens in interconnecting lines. Integr. 42(3): 286-293 (2009) - [j32]Luz Balado, Emili Lupon
, Joan Figueras, Miquel Roca, Eugeni Isern
, Rodrigo Picos
:
Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(4): 754-762 (2009) - 2008
- [j31]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras:
Experimental Characterization of CMOS Interconnect Open Defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 123-136 (2008) - [c64]Rosa Rodríguez-Montañés, Daniel Arumí
, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Time-dependent Behaviour of Full Open Defects in Interconnect Lines. ITC 2008: 1-10 - [c63]Francesc Moll
, Joan Figueras, Antonio Rubio:
Data Dependence of Delay Distribution for a Planar Bus. PATMOS 2008: 409-418 - [c62]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Full Open Defects in Nanometric CMOS. VTS 2008: 119-124 - 2007
- [j30]Salvador Manich
, Lucas Garcia-Deiros, Joan Figueras:
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2046-2058 (2007) - [c61]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi:
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. VTS 2007: 145-150 - [c60]Rosa Rodríguez-Montañés, Daniel Arumí
, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi:
Diagnosis of Full Open Defects in Interconnecting Lines. VTS 2007: 158-166 - 2006
- [c59]Luz Balado, Emili Lupon
, L. García, Rosa Rodríguez-Montañés, Joan Figueras:
Lissajous Based Mixed-Signal Testing for N-Observable Signals. DDECS 2006: 125-130 - 2005
- [j29]R. Sanahuja, Victor Barcons
, Luz Balado, Joan Figueras:
Testing Biquad Filters under Parametric Shifts Using X-Y Zoning. J. Electron. Test. 21(3): 257-265 (2005) - [c58]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras:
Defective behaviours of resistive opens in interconnect lines. ETS 2005: 28-33 - 2004
- [j28]Rosa Rodríguez-Montañés, D. Muñoz
, Luz Balado, Joan Figueras:
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. J. Electron. Test. 20(2): 143-153 (2004) - [j27]Marcelino B. Santos
, Isabel C. Teixeira
, João Paulo Teixeira
, Salvador Manich
, Luz Balado, Joan Figueras:
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electron. Test. 20(4): 345-355 (2004) - [c57]Victor Avendaño, Víctor H. Champac, Joan Figueras:
Signal integrity verification using high speed monitors. ETS 2004: 114-119 - [c56]Salvador Manich
, L. García, Luz Balado, Emili Lupon
, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
BIST Technique by Equally Spaced Test Vector Sequences. VTS 2004: 206-216 - 2003
- [c55]Salvador Manich
, L. García, Luz Balado, Emili Lupon
, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
On the selection of efficient arithmetic additive test pattern generators [logic test]. ETW 2003: 9-14 - [c54]Victor Avendaño, Víctor H. Champac, Joan Figueras:
Signal integrity loss in bus lines due to open shielding defects. ETW 2003: 79-84 - [c53]Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo
, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich, Jean-Pierre Van der Heyden:
Test Engineering Education in Europe: the EuNICE-Test Project. MSE 2003: 85-86 - 2002
- [j26]Antoni Ferré, Joan Figueras:
Leakage power bounds in CMOS digital technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 731-738 (2002) - [c52]Rosa Rodríguez-Montañés, D. Muñoz
, Luz Balado, Joan Figueras:
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. IOLTW 2002: 99-103 - [c51]Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras:
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC 2002: 814-823 - [c50]Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras:
On High-Quality, Low Energy BIST Preparation at RT-Level. LATW 2002: 52-57 - 2001
- [j25]Antonio Zenteno, Víctor H. Champac, Joan Figueras:
Detectability Conditions of Full Opens in the Interconnections. J. Electron. Test. 17(2): 85-95 (2001) - [j24]Paolo Prinetto, Joan Figueras:
Guest Editorial. J. Electron. Test. 17(3-4): 207 (2001) - [j23]Antoni Ferré, Joan Figueras:
LEAP: An Accurate Defect-Free IDDQ Estimator. J. Electron. Test. 17(3-4): 267-274 (2001) - [j22]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electron. Test. 17(3-4): 283-290 (2001) - [j21]Anna Maria Brosa, Joan Figueras:
Digital Signature Proposal for Mixed-Signal Circuits. J. Electron. Test. 17(5): 385-393 (2001) - [c49]Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931 - [c48]Anotnio Zenteno, Víctor H. Champac, Joan Figueras:
Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain. LATW 2001: 38-44 - [c47]Joan Figueras:
Test Challenges in a Nanometric World. LATW 2001: 209 - 2000
- [j20]Salvador Manich
, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira
, Marcelino B. Santos
:
Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. 16(3): 193-202 (2000) - [j19]Anna Maria Brosa, Joan Figueras:
On Maximizing the Coverage of Catastrophic and Parametric Faults. J. Electron. Test. 16(3): 251-258 (2000) - [j18]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electron. Test. 16(3): 289-299 (2000) - [j17]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electron. Test. 16(5): 513-520 (2000) - [c46]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328 - [c45]Antoni Ferré, Joan Figueras:
LEAP: An accurate defect-free IDDQ estimator. ETW 2000: 33-38 - [c44]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Analyzing the test generation problem for an application-oriented test of FPGAs. ETW 2000: 75-80 - [c43]Anna Maria Brosa, Joan Figueras:
Digital signature proposal for mixed-signal circuits. ITC 2000: 1041-1050 - [c42]Antonio Zenteno, Víctor H. Champac, Joan Figueras:
Detectability Dependency on Test Generation Process for Interconnection Opens. LATW 2000: 47-53 - [c41]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test Configuration Generation for FPGA Logic Cells. LATW 2000: 202-208 - [c40]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. SBCCI 2000: 3-8
1990 – 1999
- 1999
- [j16]Anna Maria Brosa, Joan Figueras:
Characterization of Floating Gate Defects in Analog Cells. J. Electron. Test. 14(1-2): 23-31 (1999) - [j15]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electron. Test. 14(1-2): 159-167 (1999) - [j14]Víctor H. Champac, José Castillejos, Joan Figueras:
IDDQ Testing of Opens in CMOS SRAMs. J. Electron. Test. 15(1-2): 53-62 (1999) - [c39]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368 - [c38]Josep Rius, Joan Figueras:
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. DATE 1999: 543-548 - [c37]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622 - [c36]Anna Maria Brosa, Joan Figueras:
On maximizing the coverage of catastrophic and parametric faults. ETW 1999: 123-128 - [c35]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. ETW 1999: 146-151 - [c34]Salvador Manich
, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low power BIST by filtering non-detecting vectors. ETW 1999: 165-170 - [c33]Anna Maria Brosa, Joan Figueras:
On Optimizing Test Strategies for Analog Cells. Great Lakes Symposium on VLSI 1999: 92-96 - [c32]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos:
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113 - 1998
- [j13]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Interconnect of RAM-Based FPGAs. IEEE Des. Test Comput. 15(1): 45-50 (1998) - [j12]Antoni Ferré, Eugeni Isern
, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
IDDQ testing: state of the art and future trends. Integr. 26(1-2): 167-196 (1998) - [c31]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271 - [c30]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88 - [c29]Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi:
Novel Technique for Testing FPGAs. DATE 1998: 89-94 - [c28]Rosa Rodríguez-Montañés, Joan Figueras:
Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. DATE 1998: 490-494 - [c27]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148 - [c26]Antoni Ferré, Joan Figueras:
Characterization of leakage power in CMOS technologies. ICECS 1998: 185-188 - [c25]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111 - [c24]Víctor H. Champac, José Castillejos, Joan Figueras:
IDDQ Testing of Opens in CMOS SRAMs. VTS 1998: 106-111 - 1997
- [j11]Michael Nicolaidis, Ricardo de Oliveira Duarte
, Salvador Manich
, Joan Figueras:
Fault-Secure Parity Prediction Arithmetic Operators. IEEE Des. Test Comput. 14(2): 60-71 (1997) - [j10]Eugeni Isern
, Joan Figueras:
IDDQ Detectable Bridges in Combinational CMOS Circuits. VLSI Design 5(3): 241-252 (1997) - [j9]Víctor H. Champac, Joan Figueras:
Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects. VLSI Design 5(3): 273-284 (1997) - [c23]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254- - [c22]Salvador Manich, Joan Figueras:
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. ED&TC 1997: 597-602 - [c21]Antoni Ferré, Joan Figueras:
IDDQ Characterization in Submicron CMOS. ITC 1997: 136-145 - [c20]Rosa Rodríguez-Montañés, Joan Figueras:
Bridges in sequential CMOS circuits: current-voltage signatur. VTS 1997: 68-73 - [c19]Michel Renovell, Joan Figueras, Yervant Zorian:
Test of RAM-based FPGA: methodology and application to the interconnect. VTS 1997: 230-237 - [c18]Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian:
Power Dissipation During Testing: Should We Worry About it? VTS 1997: 456-457 - 1996
- [j8]Rosa Rodríguez-Montañés, E. M. J. G. Bruls, Joan Figueras:
Bridging defects resistance in the metal layer of a CMOS process. J. Electron. Test. 8(1): 35-46 (1996) - [j7]Josep Rius, Joan Figueras:
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments. J. Electron. Test. 9(3): 295-310 (1996) - [c17]Michael Nicolaidis, Salvador Manich
, Joan Figueras:
Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations. ED&TC 1996: 186-194 - [c16]S. Caufape, Joan Figueras:
Power Optimization of Delay Constrained CMOS Bus Drivers. ED&TC 1996: 205-213 - [c15]Antoni Ferré, Joan Figueras:
On estimating bounds of the quiescent current for IDDQ testin. VTS 1996: 106-111 - [c14]Salvador Manich, Michael Nicolaidis, Joan Figueras:
Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring. VTS 1996: 124-129 - 1995
- [j6]Eugeni Isern, Joan Figueras:
IDDQ Test and Diagnosis of CMOS Circuits. IEEE Des. Test Comput. 12(4): 60-67 (1995) - [j5]Joan Figueras, Michel Renovell:
Current testing in dynamic CMOS circuits. J. Electron. Test. 6(1): 127-131 (1995) - [c13]Hans-Joachim Wunderlich, M. Herzog, Joan Figueras, Juan A. Carrasco, Angel Calderón:
Synthesis of IDDQ-testable circuits: integrating built-in current sensors. ED&TC 1995: 573-580 - [c12]Antonio Rubio, Edmond Janssens, H. Casier, Joan Figueras, Diego Mateo
, P. De Pauw, Jaume Segura
:
A built-in quiescent current monitor for CMOS VLSI circuits. ED&TC 1995: 581-587 - [c11]Víctor H. Champac, Joan Figueras:
Testability of floating gate defects in sequential circuits. VTS 1995: 202-207 - [c10]Josep Rius, Joan Figueras:
Detecting IDDQ defective CMOS circuits by depowering. VTS 1995: 324-329 - 1994
- [j4]Víctor H. Champac, Antonio Rubio, Joan Figueras:
Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 359-369 (1994) - [c9]Rosa Rodríguez-Montañés, Joan Figueras:
Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability. EDAC-ETC-EUROASIC 1994: 356-360 - [c8]Eugeni Isern, Joan Figueras:
Test of Bridging Faults in Scan-based Sequential Circuits. EDAC-ETC-EUROASIC 1994: 366-370 - [c7]Eugeni Isern, Joan Figueras:
Analysis of IDDQ detectable bridges in combinational CMOS circuits. VTS 1994: 368-373 - 1993
- [c6]Víctor H. Champac, Antonio Rubio, Joan Figueras:
Analysis of the Floating Gate Defect in CMOS. DFT 1993: 101-108 - [c5]Michel Renovell, Joan Figueras:
Current Testing Viability in Dynamic CMOS Circuits. DFT 1993: 207-214 - [c4]Eugeni Isern
, Joan Figueras:
Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits. ITC 1993: 73-82 - [c3]Eugeni Isern, Joan Figueras:
Analysis of redundant structures in combinational circuits. VTS 1993: 21-23 - 1992
- [j3]Jaume A. Segura
, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio:
Quiescent current analysis and experimentation of defective CMOS circuits. J. Electron. Test. 3(4): 337-348 (1992) - [j2]Josep Rius, Joan Figueras:
Proportional BIC sensor for current testing. J. Electron. Test. 3(4): 387-396 (1992) - [c2]Rosa Rodríguez-Montañés, Joan Figueras, Eric Bruls:
Bridging Defects Resistance Measurements in a CMOS Process. ITC 1992: 892-899 - 1991
- [j1]Juan A. Carrasco, Joan Figueras, Annie Kuntzmann-Combelles:
Evaluation of safety-oriented two-version architectures. J. Syst. Softw. 14(3): 155-162 (1991) - [c1]Rosa Rodríguez-Montañés, Jaume A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio:
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. ITC 1991: 510-519
Coauthor Index
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For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
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Citation data
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load citations from opencitations.net
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OpenAlex data
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last updated on 2024-05-08 20:56 CEST by the dblp team
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