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ORCIDAPCCAS 2024: Taipei, Taiwan
- IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2024, Taipei, Taiwan, November 7-9, 2024. IEEE 2024, ISBN 979-8-3503-7877-1
- Pang-Yen Ko, Shuenn-Yuh Lee:
Live Demonstration: A Study on Monitoring Canine Emotional Changes through Heart Rate Variability. 1 - Wei-Chi Huang, Chen-Fu Yeh, Po-An Chen, Yu-Chih Tsai, Kea-Tiong Tang:
Live Demonstration: Low Power and Real-Time Obstacle Avoidance System with CMOS Image Sensor and Spiking Neural Network. 1 - Chenyi Zhu, Quan Yin, Jigui Miao, Jindian Chen:
The Intermittent Fault Diagnosis of Analog Circuits Based on EMD-CrossFormer. 1-5 - Hsu-Chi Chen, Pin-Ching Shen, Yen-Chen Yen, Ying-Yu Wang, Kun-Chih Jimmy Chen:
NoC AI Chip Integration for Industrial IoT Fault Diagnosis and Notification System. 1 - Bo-An Shi, Shuenn-Yuh Lee:
Live Demonstration: AI-Based Arrhythmia Detection with Wearable ECG and Cloud Platform for Dog Health Monitoring. 1 - George Wu, Chi-Tsun Cheng, Toh Yen Pang:
Live Demonstration: Defect Detection in Material Extrusion with Multimodal Large Language Model. 1 - Zhan-Xian Liao, Yu-Kai Kang, Shuenn-Yuh Lee, Chou-Ching K. Lin:
Live Demonstration: Portable Stimulation System for Transcutaneous Auricular Vagus Nerve Stimulation. 1 - Ching-Yao Chen, Meng-Chieh Chen, Tian-Sheuan Chang:
VESTA: A Versatile SNN-Based Transformer Accelerator with Unified PEs for Multiple Computational Layers. 6-10 - Yu-Chuan Lin, Kuen-Jong Lee:
A Lightweight Memory Protection Scheme with Criticality-Aware Encryption and Embedded MAC for Secure DNN Accelerators. 11-15 - Minji Shon, Junmo Lee
, Shimeng Yu:
3D Digital Compute-in-Memory Benchmark with A5 CFET Technology. 16-19 - Chenxi Feng, Xingbo Wang, Terry Tao Ye:
Low-Power Consumption Inference of ECG Signals Using Differential Logic Networks. 20-24 - Ivan Miro-Panades, Vincent Lorrain, Lilian Billod, Inna Kucher, Vincent Templier, Sylvain Choisnet, Nermine Ali, Baptiste Rossigneux, Olivier Bichler, Alexandre Valentian:
A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS. 25-29 - Cheng-Yang Chang, Chi-Tse Huang, An-Yeu Andy Wu:
DIET-PIM: Dynamic Importance-based Early Termination for Energy-Efficient Processing-in-Memory Accelerator. 30-34 - Oscal Tzyh-Chiang Chen, Yun-Chia Hsu, Tun-Sheng Yang:
Detecting Speech Deepfakes through Improved Speech Features and Cost Functions. 35-39 - Lan-Da Van, Yi-Ho Wang, Shen-Jui Huang, Sau-Gee Chen:
A Low-Complexity Reconfigurable FFT Processor for Four Data Overlapping Modes. 40-44 - Fanyang Li, Zhanpeng Yuan, Faxiang Wang:
LD-MDCT Quantization Algorithm Optimization and FPGA Realization Using DUTSQ and SFDP Techniques. 45-49 - Dong Cui, Takayuki Kawahara:
Proposal and Validation of Annealing-processor-calculation Method Using Error-diffusion Rounded Interaction Matrix. 50-54 - Kazuma Kanai, Takayuki Kawahara:
Efficient Implementation of Parallel Annealing Method with Heisenberg Model. 55-59 - Ying-Tzu Chen, Wei-Kai Cheng:
Global Routing Optimization Analysis based on Deep Reinforcement Learning. 60-63 - Mugi Noda, Nagisa Ishiura:
Enumeration of Genaralized Parallel Counters for Multi-Input Adder Synthesis for FPGAs. 64-68 - Jinn-Shyan Wang, Yong-Chin Miu, Chia-Hua Wu:
In-Situ Critical-Path Replica for Variation-Aware Low-Power Designs with Timing Margin Detection. 69-73 - Dong-Yi Chen, Cheng-Hong Lee, Kuen-Jong Lee, Nan-Hsin Tseng, Hsin-Wei Hung, Hao-Yu Yang:
An On-chip High-resolution Delay Measurement Scheme for TSVs in 3DIC. 74-78 - Rui Wang, Jin Li, Bo Chen, Tao Yuan:
A Transient-Enhanced Dual-Loop Low-Dropout Linear Regulator in 65-nm SOI CMOS With <1-μs Settling Time for 5G Applications. 79-82 - Techapon Songthawornpong, Amorn Jiraseree-amornkun, Thaweesak Thantipwan, Woradorn Wattanapanitch:
A Low-Noise Fully-Differential Bandgap Reference for Low-Power High-Precision ADCs. 83-86 - Vincent Angelo Bogg's G. Roxas, Ralph Maru M. Grande, Maria Sophia C. Ralota, Rafael M. Pangilinan, Arcel G. Leynes, Maria Theresa G. de Leon:
A Low-Power Fully-Differential Chopper-Stabilized LNIA in 22nm FD-SOI for MEMS-based Thermopile Sensors. 91-94 - Sujal Reddy Kariveda, Suraj Kumar Prusty, Nijwm Wary:
Machine Learning based Adaptation for CTLE of Serial Links. 95-99 - N. Rakesh, R. S. Ashwin Kumar:
Low Noise Low Power Readout Circuit For Capacitance Based MEMS Accelerometers. 100-104 - Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A Wireless Data and Power Transfer-Enabled MCU for Shape-Configurable Chiplet-Based Computers. 105-109 - Chao Wang, Yunxiang Zhang, Wangzilu Lu, Jiajie Huang, Qing Zhang, Minghui Yin, Yuhang Zhang, Zhiqiang Li, Yongfu Li:
D2D-GPT: Leveraging Incremental Learning GPT for Seamless Design Rule Conversion Across EDA Tools. 110-114 - Zehua Yin, Bingqiang Liu, Jipeng Wang, Zixuan Shen, Guangyao Li, Chao Wang:
A low-hardware-overhead, high-energy-efficiency, and end-to-end CNN-based feature extraction accelerator for mobile visual SLAM. 115-119 - Zhou Wang, Haochen Du, Jiuren Zhou, Yanqing Xu, Xiaonan Tang, Tianchun Ye, Shaojun Wei, Shushan Qiao, Shouyi Yin:
SSPE: A Device-edge SNN Inference Artificial Intelligence Processor in Supporting Smart Computing. 120-124 - Zixiong Feng, Zhongfeng Wang, Wendong Mao:
A Precision-Scalable Energy-Efficient DNN Accelerator for Robotic Grasping. 125-129 - Ning Zhao, Jiayuan Chen, Jingjing Lv, Chenjia Xie, Yuan Du, Li Du:
A Streaming Transformer Accelerator with Efficient On-Chip Normalization. 130-134 - Zhaohao Wang, Chao Wang, Min Wang, Chenyi Wang, Kaihua Cao, Chenlin Xu, Cong Zhang, Yunpeng Li, Hongxi Liu:
Process and Design Considerations for Spin Orbit Torque MRAM. 135-139 - Xiapeng Xu, Yongteng Ma, Xuliang Yu, Fanzi Meng, Wei-Han Yu, Liang Zhao:
A 10-bit Two-Stage Pipeline SAR ADC in 55nm CMOS for Compute-in-Memory Applications. 140-143 - Yung-Cheng Lai, Chin-Fu Nien:
An Automated Design Platform for ReRAM-based DNN Accelerators with Hardware-Software Co-exploration. 144-148 - Yu-Tzu Chen, Chin-Fu Nien, Chin Hsia, Chung-Yi Li:
Interactive Analog IC Layout Tool with Real-time Parasitic-aware Automatic Routing Assistance. 149-153 - Yi-Hua Chen, Pin-Jung Chen, Yu-Pei Liang, Yuan-Hao Chang, Wei-Kuan Shih:
Optimizing N-Degree Union Problems in Graph Data Processing for Enhancing the Efficiency of Dynamic Graphs. 154-158 - Che-Min Chen, Yi-Chao Shih, Xin Liu, Wei-Kuan Shih, Tseng-Yi Chen:
Implementing Content-Defined Chunking for Deduplication in Host-Managed SSDs. 159-163 - Zih-Cing Pan, Yi-Chao Shih, Xin Liu, Yu-Pei Liang, Yuan-Hao Chang, Wei-Kuan Shih:
Enabling a deleted-key-value-aware garbage collection strategy for LSM-tree on OCSSD. 164-168 - Mingyuan Ma, Wei Jiang, Juntao Liu, Li Du, Zhongyuan Ma, Yuan Du:
A Resource-Efficient Weight Quantization and Mapping Method for Crossbar Arrays in ReRAM-based Computing-in-Memory Systems. 169-173 - Ting-An Lin, Po-Tsang Huang:
Design Exploration of In-Situ Error Correction for Multi-Bit Computation-in-Memory Circuits. 174-178 - Kun-Chih Jimmy Chen, Ting-En Kao, Li-Heng Ke:
TPE: Trajectory Path Encoding for Anonymous Routing Algorithm in NoC-based Systems. 179-182 - Akiho Kawada, Kenji Kobayashi, Jaewon Shin, Rei Sumikawa, Mototsugu Hamada, Atsutake Kosuge:
A 250.3μW Versatile Sound Feature Extractor Using 1024-point FFT 64-ch LogMel Filter in 40nm CMOS. 183-187 - Kuanyu Gu, Zhan Ning, Likai Li, Jingjing Lv, Zhong Zhang, Li Du, Yuan Du:
A 500MHz, 0.5% THD With 400mVpp Linear Transimpedance Amplifier (TIA) for Analog Optical and In-memory Computing Applications. 188-192 - Sezin Kircali Ata, Zhi-Hui Kong, Anusha James, Lile Cai, Kiat Seng Yeo, Khin Mi Mi Aung, Chuan Sheng Foo, Ashish James:
Towards Safe and Efficient Analog Circuit Design: Active Learning for Feasibility Region Exploration. 193-197 - Haihang Zhao, Anyu Cheng, Yi Wang, Shanshan Wang, Hongrong Wang:
CAN Intrusion Detection System Based on Data Augmentation and Improved Bi-LSTM. 198-202 - I-Lun Tseng:
Pragmatic EDA Flow Runtime Prediction with Machine Learning and Automatic Outlier Removal. 203-207 - Tai-Lai Liu, Chansyun Yang, Yu-Ju Chuang, Herming Chiueh:
Radiation-hardened Configuration Registers with SPI Interface Protocol in a 65nm CMOS Technology. 212-216 - Ming-Hao Chang, Chansyun Yang, Yu-Ju Chuang, Herming Chiueh:
A Radiation-Hardened Serial Peripheral Interface with an ECC-Protected SRAM in a 65nm CMOS Technology. 217-220 - Chen-Ho Chen, Chien-Nan Jimmy Liu, Wei-Ting Tu, Tung-Chieh Chen, Iris Hui-Ru Jiang:
Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques. 221-225 - Zirui Wang, Renhe Chen, Yu Gu, Albert Lee, Di Wu, Xufeng Kou:
A Lightweight Post-Processing Method for Voltage-Controlled MTJ based True Random Number Generator. 226-230 - Ryoma Katsube, Taiki Nagatomo, Tomoaki Ukezono:
Flattening Power Waveforms by Hamming Distance Converter for Side-channel Attacks. 231-235 - Tung-Chun Wu, Rung-Bin Lin:
Standard Cells with Inverted Inputs in 7nm Technology. 236-240 - Wenhao Wu, Fei Yuan, Yushi Zhou:
Sub-Threshold Delay-Locked Loop with Piecewise Linearization and Time-Mode Proportional-Integral Locking. 241-245 - Haonan Fan, Jiahao Liu, Wangchen Fan, Weifeng Sun, Zhongyuan Fang:
An Error Amplifier With Enhanced Slew Rate and Clamp Function Supporting Multi-Mode Control of Four-Switch-Buck-Boost Converter. 246-250 - Yukinojo Kotani, Yoko Uwate, Yoshifumi Nishio:
Analysis of Complex Behaviors on Memristor - Based Bonhöeffer van der Pol Oscillator. 251-255 - Jinhen Lee, Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang:
A Novel Voltage-Controlled Oscillator Linearized by a Resistorless Dynamic-Degeneration Technique. 256-260 - Hyeonmin Park, Ahryung Kim, Jeyeon Lee, SeongHwan Cho:
A Stochastic RMS Jitter Monitoring Circuit for Clock Generators using Central Limit Theorem. 261-264 - Tzung-Je Lee, Ruei-Chi Lai, Aleksandr Vasjanov, Vaidotas Barzdenas:
A 23.9 ppm/°C Bandgap Reference Circuit with Wide Temperature Range Using Subthreshold PVT Detector. 265-268 - Hao-Wei Wu, Chung-Yuan Wang, Huan-Jhong Chen, Yi-Cheng Lin, Ping-Hsuan Hsieh, Fan-Yi Lin, Yuan-Hao Huang, Po-Chiun Huang:
A CMOS Transimpedance Amplifier Accommodating Wide CPD and Input Bias Range for Chaos Lidar. 269-272 - Hao-Yu Luo, Yi-Fan Tsao:
A High-Power Single-Pole-Double-Throw Switch with High Isolation for Millimeter-wave Satellite Applications. 273-276 - Sheng-Lyang Jang, Shih-Hsuan Chen, Jiun-Yu Sung, Wen-Cheng Lai, Mao-Hsiu Hsu, Miin-Horng Juang:
VCO with 8-shaped Transformer Coupled Transmission-Line. 277-280 - Ming-Hsuan Kuo, Yi-Hsuan Hsia, Kuang-Wei Cheng:
Low Power Low Noise and High Sensitivity FSK/OOK Wake-Up Receiver. 281-285 - Hao-Yu Luo, Yi-Fan Tsao:
A Highly-Efficient Power Amplifier for V-band Inter-Satellite Link Applications. 286-289 - Yan-Ming Chang, Hsiao-Chin Chen, Chun-Hsuan Fan:
A 18.8 GHz Noise Circulating VCO With Implicit Noise Filter for Quantum Computing. 290-292 - Pei-Hsuan Wang, Yi-Cheng Liu, Yu-Yuan Huang, Wei-Show Hsu, Yu-Li Hsueh, Yuan-Hung Chung, Tsung-Hsien Lin:
An 80-GHz Phase-Locked Loop for MillimeterWave Application in 40-nm CMOS. 293-296 - Shiela Cabahug, Chia-Cheng Hsieh, Yi-Wei Wang, Ti-Wei Hsu, Yuan-Hsiang Lin:
The Flight Motion Measurement of Yamawaki on Horizontal Bar. 297-300 - Zheng-Lin Chen, Chao-Ting Huang, Bo-Ruei Huang, Yu-Feng Lin, Ting-Yu Lin, Kun-Lin Tsai, Chi-Chia Sun:
Optimizing Computational Efficiency: A Novel Approach through XOR-logic Operation in In-Memory Computing. 301-305 - Novendra Setyawan, Chi-Chia Sun, Wen-Kai Kuo, Mao-Hsiu Hsu:
FPGA-Based Batik Classification Using Quantization Aware Training of MobileNet and Data-flow Implementation. 306-310 - Andreas Kitzig, Edwin Naroska, Shanq-Jang Ruan, Marcus Weberskirch, Sinan Yavuz:
RUBY - A versatile and customizable social robot. 311-315 - Jianchan Yang, Chin Hsia, Deng-Fong Lu:
Integrated All-GaN Driver for Non-isolated Resonant Converters. 316-319 - Junita Sari, Ting Yue, Liang Chang:
The Light-Weighted Road Fault Identification for Embedded Hardware Platform Using YOLO. 320-324 - Chang-Yu Wu, Song-Min Ke, Hoh-Siang Liao, Chen-Hua Chen, Ying-Hsiu Hung, Shin-Chi Lai:
Insect Classification Using Spatial Pyramid Pooling and Convolution Neural Network. 325-329 - Chenyang Han, Yujun Shu, Tianwei Li, Jiangfeng Wu, Yongzhen Chen:
A BJT-Based Temperature Sensor Achieving an Inaccuracy of ±0.3°C (3σ) and a 6.605 pJ∙K2 Resolution FoM in 28-nm CMOS. 330-334 - Yung-Han Tseng, Yi-Cheng Lin, Sheng-Che Lin, Ping-Hsuan Hsieh, Cheng-Ting Lee, Chih-Hao Chang, Fan-Yi Lin:
A Switched-Capacitor Cross-Correlation-Based Time-of-Flight Design for Pulsed Chaos Lidar Systems. 335-338 - Chien-Cheng Tseng, Su-Ling Lee:
Design of Hermite Polynomial Graph Filter and Its Application to Sensor Network Data Denoising. 339-343 - Zheyi Li, SinNyoung Kim, Reza Tavakoli Dinani, Yijing Zhang, Ilker Eryilmaz, Laurent Berti, Milos Nesladek:
Miniaturized Laser Diode Driver and Microwave Source for Transportable Quantum Sensors. 344-348 - Pin-Hao Tung, Geng-Shi Jeng, Bo-Cheng Lai, Yu-Xiang Hung:
Automated Optimization for FPGA-Based Sonar Object Recognition Systems. 349-353 - Zu-Jia Lo, Yi-Wei Peng, Ming-Hsuan Tsai, Sheng-Yu Peng:
An Eight-Channel Analog Front-End Circuitry for the Application of Neural Signal Sensing. 354-357 - Tawfik Rahal-Arabi, Paul Van der Arend, Ashish Jain, Mehdi Saidi, Rashad Oreifej, Sriram Sundaram, Srilatha Manne, Indrani Paul, Rajit Seahra, Frank Helms, Esha Choukse, Nithish Mahalingam, Brijesh Warrier, Ricardo Bianchini:
Optimizing GPU Data Center Power. 358-362 - Ryunosuke Numata, Toshimichi Saito:
Biobjective Optimization Problems in a Simplified Model of Boost Converter with Photovoltaic Input. 363-367 - Chih-Chiang Wu, Pan-Hsiang Hsieh, Shin-Hung Chang:
Experimental evaluation of an integrated traction inverter used on an electric vehicle platform. 368-371 - Shang-Chih Yin, Po-Ju Chen, Shang-Chien Yang, Chien-Hung Tsai:
Model-Based Design Methodology for Non-Inverting Buck-Boost Converter with Enhanced Duty Overlap Control and DVS. 372-376 - Chih-Chiang Wu, Uma Sankar Rout, Yu-Long Wang, Yi-Ling Lin, Jwu-Sheng Hu:
A Comparative Analysis of SiC MOSFET Performance in a Traction Inverter. 377-381 - Peijuan Ju, Qisong Wu, Dixian Zhao:
Multiple-Loop Analysis and Design for Fast-Transient Capacitor-less LDO with Dual-Path Compensation and Zero-Pole placement in 65-nm CMOS. 382-386 - Huayue Song, Lei Qian, Guangzu He, Yongfu Li, Yan Liu:
An Incremental Zoom ADC With Quantization Level Shifting Technique For Over-Ranging Reduction. 387-391 - Yuki Sasaki, Takuro Noguchi, Yohei Ishikawa, Sumio Fukai, Akio Shimizu:
A Micro-phase Difference Measurement Circuit Using 4-bit Input Stage. 392-396 - Zi-Chi Lin, Chun-Yang Chiu, Yung-Hui Chung:
A 91.7-dB SNDR Discrete-Time Zoom ADC with a 20-kHz BW in 180-nm CMOS. 397-400 - Maximilian Scherzer, Mario Auer:
A 4 Bit Segmented Current-Steering Harmonic-Cancelling Digital-to-Analog Converter for High Frequency Sine-Wave Synthesis. 401-405 - Chia-Wei Liu, Yi-Ting Hsieh, Shuenn-Yuh Lee, Ju-Yi Chen:
A Second-Order Noise Shaping SAR ADC with Fully Passive Integrators and Pole Optimization. 406-409 - Seiji Komatsu, Takayuki Kawahara:
Method for Measuring Silicon Quantum Dots with TMR Sensor. 410-413 - Zhongzhiguang Lu, Hanchao Li, Yihao Zhuang, Hanlin Xie, Geok Ing Ng, Yuanjin Zheng:
An ANN-Physical Hybrid GaN HEMT Model for 5G Power Amplifiers. 414-418 - Zijie Hu, Yongfu Li, Koen Mouthaan:
2-16 GHz Phase Shifter With Continuous 435° Phase-Control in 130 nm CMOS. 419-423 - Joscha Ilmberger, Niels Fiedler, Andreas Grübl, Johannes Schemmel:
A flexible multi-standard I/O interface for chip-to-chip links in 65 nm CMOS. 424-427 - Liang-Wei Ouyang, Clint Sweeney, Jill C. Mayeda, Donald Y. C. Lie, Jerry Lopez:
A Mm-Wave 5G Broadband Power Amplifier with Subthreshold Adaptive Biasing Network in 22 nm FD-SOI CMOS. 428-431 - Yao-Wei Huang, Yu-Te Liao:
A 62nW, 920MHz Wake-up Receiver with Automatic Offset Calibration Technique. 432-436 - Brandon P. Hippe, David C. Burnett:
Digital Baseband Architecture and Simulated Low-IF FSK Receiver Performance. 437-441 - Armin Darjani, Nima Kavand, Akash Kumar:
Toward Structurally Safe Design-for-Trust Techniques. 442-446 - Gokulnath Rajendran, Suman Deb, Anupam Chattopadhyay:
PUF-based Lightweight Authentication for Binarized Neural Networks. 447-451 - Soumik Sinha, Sayandeep Saha, Ayantika Chatterjee, Debdeep Mukhopadhyay:
FHEDGE: Encrypted Inference on Lightweight Edge Devices. 452-456 - Anirban Kar, Yogesh Singh Chauhan, Hussam Amrouch:
Innovations in Hardware Security: Leveraging FeFET Technology for Future Opportunities. 457-460 - Martin Schmid, Tolga Arul, Elif Bilge Kavun, Francesco Regazzoni, Orhun Kara:
Robust and Energy-efficient Hardware Architectures for DIZY Stream Cipher. 461-465 - Jitendra Bhandari, Jayanth Gopinath, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri:
Safeguarding the Silicon: Strategies for Integrated Circuit Layout Protection. 466-470 - Xinyu Kang, Silong Li, Xingbo Wang, Zhiyuan Xu, Yuru Li, Terry Tao Ye:
Computation Complexity Reduction Based on Quick Leaky-Integrate-And-Fire Mechanism for SNNs. 471-474 - Qun-Kai Lin, Cheng Hsu, Tian-Sheuan Chang:
Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering Techniques. 475-478 - Oratai Nikornpon, Pichaya Chaipanya:
Predicting Beam Switching Directions in Ultra Wideband Spiral Antennas Using Machine Learning Algorithms. 479-483 - Worakan Noimi, Pichaya Chaipanya:
Wide-band Circular Slot Antenna Beam Switching Directions Using Machine Learning Algorithms. 484-488 - Akhila Remanan, Vineeta Vasudevan Nair, Sruthi Pallathuvalappil, Alex Pappachen James:
Analog Neuron as Generalised Similarity Metric. 489-493 - Ryuhei Michizoe, Hiroko Kinosada, Hiroki Nishikawa, Ittetsu Taniguchi, Kazuhide Matsunaga, Narikazu Uzawa, Takao Onoye:
Japanese Vowel-mora Visualization for Dysarthria Rehabilitation with Variational Autoencoder. 494-498 - Qinxuan Xiang, Guangzheng Yu, Yijing Chu, Ming Wu, Yuezhe Zhao:
A Multi-Channel Decoupling Method for Feedforward Active Noise Control Using Neural Networks. 499-503 - Infall Syafalni, Muhammad Sulthan Mazaya, Muhammad Raihan Elfazri, Eko Mursito Budi, Nana Sutisna, Rahmat Mulyawan, Trio Adiono, Makoto Ikeda:
Design of Extended RISC-V for Q-Learning Hardware Accelerator using HW/SW Co-Design. 504-508 - Tomohiro Yoshita, Junichiro Kadomoto, Hidetsugu Irie:
A Dynamic Approximation Processor Based on Out-of-Order RISC-V in 28-nm CMOS. 509-513 - Zhao Cui, Jing Tian:
LEAM: A Low-Area and Efficient Accelerator of Matrix-Vector Multiplication for Homomorphic Encryption. 514-518 - Tien-Min Chang, Chung-An Shen:
The VLSI Architecture Design of a Configurable and High-Throughput Singular Value Decomposition Processor. 519-523 - Sambhav Sharma, Garima Choudhary, Neha Gupta, Sunil Rathore, Anand Bulusu, Sudeb Dasgupta:
TG-in-DRAM: A Transmission Gate based Full Adder using Multi-row Activation for enhanced Throughput in CIM Architectures. 524-528 - Muhammad Izzatul Fauzan Hasibuan, Raihan Fadhil Yanuarsyah, Muhammad Hanif Hibatullah, Radithya Arisaputra, Infall Syafalni, Nana Sutisna, Trio Adiono, Makoto Ikeda:
Physical Design of RISC-V based System-on-Chip using OpenLane. 529-533 - Apurv Pandey, Naveen Kadayinti:
TRNG Based on Multiple Entropy Sources Using CTDSM. 534-538 - Keerthija Puli, Vikramkumar Pudi:
Design of Novel Systolic Array based NTT for CRYSTALS-Kyber scheme. 539-543 - Byung-Kwon An, Tony Tae-Hyoung Kim:
Reference-Free Dual-Mode Cell-to-Cell Sensing for Area-Efficient Resistive Memory. 544-548 - Jui-Ting Lin, Yi Hsin Liao, Meysam Akbari, Kea-Tiong Tang:
A 0.9 V Adaptive Sampling Rate Differential Level Crossing-SAR ADC for Biomedical Signal Acquisition System. 549-553 - Bo-Xun Hong, Tsung-Heng Tsai:
A Hybrid Voltage-Time Dual-Slope Capacitance-to-Digital Converter With Noise Shaping for Extracellular Vesicle Sensing Systems. 554-557 - Wisaroot Sriitsaranusorn, Yuki Nakanishi, Takaya Hattori, Kuang-Chih Tso, Kenzo Shodo, Hironari Takehara, Yoshinori Sunaga, Makito Haruta, Hiroyuki Tashiro, Yasuo Terasawa, Jun Ohta, Kiyotaka Sasagawa:
Charge-Pump-Circuit Implementation for Increasing Sink Current in Low-Volage CMOS Retinal-Prosthesis Chips. 558-561 - Zeyu Lu, Weijian Chen, Xu Liu:
A High-voltage Tolerant and Current-accurate Neural Stimulator Based on A Low-voltage CMOS Process. 562-565 - Zhenghang Gao, Shiwei Wang, Mingyi Chen:
A 32-bit Two-step Incremental-ADC with 125.6 dB Dynamic-range for Non-invasive BCI Applications. 566-570 - Shirui Sheng, Kwen-Siong Chong, Jun-Sheng Ng, Zhiping Lin, Joseph S. Chang, Bah-Hwee Gwee:
An Energy-Efficient and High-Accuracy Spiking Neural Network Utilizing Asynchronous CORDIC for On-FPGA STDP Learning. 571-575 - Yifan Chen, Guangzu He, Lei Qian, Yongfu Li, Yan Liu:
A Readily Driven Zoom ADC with Least-Significant Bit First Quantization for Brain-Computer Interface. 576-580 - Zhan-Xian Liao, Yu Kai Kang, Shuenn-Yuh Lee, Chou-Ching K. Lin:
A Portable Electrical Stimulation System with User Interface for Multiple tVNS Treatment. 581-584 - Takato Masuda, Yasuhiro Takahashi:
Low-power and Small-area Transimpedance Amplifier with Active Inductor in 65 nm CMOS. 585-589 - Priyadharshini Prabaharan, Sankaran Aniruddhan:
A 12 dBm, 0.1-12 GHz Compact Power Mixer based Ultra-Wideband Transmitter. 590-594 - Shoya Nagata, Yasuhiro Takahashi:
A Design of PUF Circuit Using Adiabatic Logic. 595-598 - Jiaming Liu, Yasuhiro Takahashi:
Design of Low-Power 6T Adiabatic PUF Circuit. 599-603 - Yanshen Luo, Jingci Yang, Yongfu Li, Yanhan Zeng:
A 1.3 nW, 0.014 %/V and Dual-output CMOS Voltage Reference with Self-biased Current Source. 604-608 - Zihong He, Huiwen Shi, Yongfu Li, Yanhan Zeng:
A 348-nW, 10.5-bit Analog Front End with Amplifier Resistor Series Loop for Acoustic Application. 609-613 - Juncheng Man, Lin Shang Hong, Ellia Tio Shu Yi, Rajesh C. Panicker:
ARIELLE: AR-based Independent and Experiential Language Learner on the Edge. 614-617 - Gotawa Aryo Prakoso, Infall Syafalni, Nana Sutisna, Rahmat Mulyawan, Nur Ahmadi, Trio Adiono, Fakhrul Zaman Rokhani:
A Novel Prediction Technique for Intermittent UWB Positioning System Using Hybrid LSTM-Trilateration. 618-622 - Adeline Kartika Tiku Putri, Muhammad Heronan Hyanda, Nur Ahmadi, Trio Adiono:
Real-Time Estimation of Respiratory Rate Using Contactless FMCW Radar with Adaptive Filtering for Various Breathing Patterns. 626-630 - Lei Cao, Yang Wei Lim, Maw Pin Tan, Fakhrul Zaman Rokhani:
Cognitive Frailty Classification Models for Older Adults in a Point-of-Care System. 631-635 - Kuei-Po Huang, Chin-Fu Nien, Yun-Ting Zhang, Cheng-Kuang Lee, Yu-Cheng Wang:
GPU-based Ising Machine for Solving Combinatorial Optimization Problems with Enhanced Parallel Tempering Techniques. 636-640 - Chih-Chung Hsu, Chia-Ming Lee, Po-Tsun Yu, Chun-Hung Sun, Kuang-Ming Wu:
OCR is All you need: Importing Multi-Modality into Image-based Defect Classification System. 641-645 - Wen-Ho Juang, Li-Chuan Hsu, Hau-Ping Chen, En-Chi Yang, Ming-Hwa Sheu:
Low-Complexity RDFT-Based Impedance Calculation for Enhanced EIS Analysis. 646-648 - Tsuyoshi Masubuchi, Nobukazu Takai:
Op-Amp sizing with large number of design variables using TuRBO. 649-653 - Junren Chen, Kanishkan Vadivel, Dawit Burusie Abdi, Priya Venugopal, Refik Bilgic, Giacomo Indiveri, Fernando García-Redondo, Dwaipayan Biswas:
Scaling NVMs in Event-Driven Architectures for Edge Inference. 654-658 - Junhao Zhang, Liang Chang:
COLEA: A Low-light Enhancement Accelerator with Memory-usage Reducing Strategy. 659-663 - Ming-Guang Lin, Jiing-Ping Wang, Yuan-June Luo, An-Yeu Andy Wu:
A 28nm 64.5TOPS/W Sparse Transformer Accelerator with Partial Product-based Speculation and Sparsity-Adaptive Computation. 664-668 - Chieh-Wen Yang, Yi-Cheng Lo, Tsung-Lin Tsai, An-Yeu Andy Wu:
Memory-Oriented Structural Pruning for Anomalous Sound Detection System on Microcontrollers. 669-673 - Yun Hu, Huifan Zhang, Pingqiang Zhou:
Quantized Optical Neural Network Based on Microring Resonators with On-Chip Modulation. 674-678 - Chengrui Li, Ning Zhao, Xiaopeng Zhang, Wei Gao, Chenjia Xie, Yuan Du, Li Du:
An Efficient On-Chip Storage Solution for CNN Accelerator Based on Self-tuning and Co-scheduling. 679-682 - Anuj Bhardwaj, Anand Mishra, Rohit Kumar Gupta:
A Novel Standard Cell Layout Methodology for Low Power IOT Applications. 683-686 - Po-Ta Chen, Pei-Yun Tsai, Sz-Yuan Lee:
Design and Implementation of Doppler Centroid Estimation with Quality Index for Real-Time SAR Imaging. 687-691 - Wen-Cheng Yang, Ting-An Jian, Yu-Cheng Lin, Rung-Bin Lin:
Engineering ASAP7 PDK with Buried Power Rail and Backside Metal Technologies. 692-696 - Yui Koyanagi, Tomoaki Ukezono:
Random Clock Gating for Side-channel Protection. 697-701 - Zhou Wang, Haochen Du, Jiuren Zhou, Yang Zhou, Xiaonan Tang, Tianchun Ye, Shaojun Wei, Shushan Qiao, Shouyi Yin:
GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence Applications. 702-706 - Koki Nagakura, Kunihiro Fujiyoshi:
An improved method for a set-pair routing problem by SAT. 707-711 - Yiyao Huang, Guolong Fu, Xianghui Zhang, Yanbo Zhang, Shubin Liu, Zhangming Zhu:
A 14.6-ENOB Second-Order Noise-Shaping SAR ADC With kT/C Noise Shifting. 712-716 - HaoYu Tian, Guolong Fu, Yuzhou Xiong, Yanbo Zhang, Shubin Liu, Zhangming Zhu:
A 14b Calibration-Free Pipelined SAR ADC Using a Single-Stage Gain Boost FIA. 717-721 - Yu-Wei Chang, Ming-Yueh Ku, Shuenn-Yuh Lee, Ju-Yi Chen:
A 10-MS/s Binary Weight-merged SAR ADC for Real-Time Health-Monitoring System Applications. 722-725 - Jeremy David Molines, Zylm Sabater, Fergie John Frange, Eugene Imbang, Vincent Angelo Bogg's G. Roxas, Maria Sophia Ralota, Arcel G. Leynes, Rafael M. Pangilinan, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon:
Design of a Low-Power LNIA-ADC Interface Circuit in 22nm FDSOI for a Thermopile Sensor in Biomedical Application. 731-735 - Tzung-Je Lee, Chien-Hsiang Chao:
A High Gain Range Low Gain Step dB-Linear Programmable Gain Amplifier with Parallel Complementary Switching Current Method. 736-739 - Chia-Min Lai, Chung-Chih Hung:
Design of a 3rd-Order 12-bit Incremental ADC for Power Monitoring Applications. 740-743 - Pradyumna Vellanki, Venkata Naveen Kolakaluri, Yun-Che Chang, L. S. S. Pavan Kumar Chodisetti, Mitch Ming-Chi Chou, Chua-Chin Wang:
Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFET. 744-748 - Trisha Isobelle V. Arboleda, Klenn Louie P. Laure, Mike Martin C. Diangco, Jefferson A. Hora, Xi Zhu:
A 88.6%-Efficient Multi-Input Capacitive-Based Energy Combiner with Adaptive Path Control for WSN-IoT Applications. 749-753 - Mike Martin C. Diangco, Jefferson A. Hora, Xi Zhu:
Triple-Band RF Energy Harvesting System Using TDM Combiner Drawing 1.5 μW in 22nm FDSOI Technology. 754-758 - Wing-Hung Ki, Yuan Yao, Chi-Ying Tsui:
Time Domain Analysis of WPT System with Parallel Resonant Secondary Stage Driving Rectifier Load. 759-762 - Yongjuan Shi, Chen Hu, Xiaosen Liu, Xun Liu, Junmin Jiang:
Methods of Reducing the Intrinsic Loss for Continuously-Scalable-Conversion-Ratio SC Converters. 763-766 - Zhiming He, Yan Lu:
An AOT-COT Dual-Mode Three-Level Buck Converter With Wide Load and Input Ranges. 767-771 - Yueh-En Huang, Sheng-Yu Peng:
A Current-Mode Electrical Stimulator with Charge Balance for Neural Stimulation Applications. 772-775 - Quang Dang Truong, Hanho Lee:
Efficient Polynomial Arithmetic and Hash Modules for ML-DSA and ML-KEM Standards. 776-780 - Hyunkyu Kang, Seokhoon Kim, Sanghyeok Moon, Youngmin Kim:
Lightweight Binary Neural Networks for Edge Devices. 781-784 - Rina Yoon, Seokjin Oh, Seungmyeong Cho, Ilpyeong Yoon, Jihwan Mun, Kyeong-Sik Min:
Memristor crossbar circuits of unconventional computing for low-power IoT devices. 785-789 - Po-Ting Chen, Shan-Chi Yu, Ing-Chao Lin:
An Efficient Sparse CNN Architecture with Index-based Kernel Transformation. 790-794 - Yun-Yin Huang, Yu-Guang Chen, Jing-Yang Jou:
TNSS: Two-Nibble Sparsity-Aware Stride-Decomposing Acceleration for Convolutional Neural Networks. 795-799 - Yi-Chen Chen, Shih-Hsu Huang:
Secure Control Logic Design for Dual Key Logic Locking. 800-803 - Mou-Wei Chang, Chun-Wei Chiu, Fang-Hao Hsiao, Hsuan-Yu Chen, Wen-Jui Wu, Yu-Te Liao:
Live Demonstration: A Soft Mist Inhaler with Sound and Motion Sensors for Improving Drug Usage Efficiency. 804 - Ming-Yueh Ku, Yi-Ting Hsieh, Jia-Jun Liu, Ju-Yi Chen, Shuenn-Yuh Lee:
Live Demonstration: An AIoT Wearable ECG Patch with Cloud Platform for Cardiac Disease Detection. 805 - Ivan Miro-Panades, Vincent Lorrain, Lilian Billod, Inna Kucher, Vincent Templier, Sylvain Choisnet, Nermine Ali, Baptiste Rossigneux, Olivier Bichler, Alexandre Valentian:
Live Demonstration: A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS. 810 - Chia-Chou Chuang, Yu-Lun Jheng, Chien Huang, Lu-Ying Huang, Pei-Yin Chen, Narn-Yih Lee:
Live Demonstration: Low Cost AES-256 Circuit Design and Application. 811
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