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ORCIDITC-Asia 2017: Taipei, Taiwan
- International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, September 13-15, 2017. IEEE 2017, ISBN 978-1-5386-3051-8
- Tim Cheng:
Keynote I: Hardware security - Verification, test, and defense mechanisms. xii-xv - Yervant Zorian:
Tutorial I: Topic: Automotive test strategies. ix-xi - Masayuki Kawabata, Koji Asami, Shohei Shibuya, Tomonori Yanagida
, Haruo Kobayashi:
Low-distortion signal generation for analog/mixed-signal circuit testing with digital ATE. 2-7 - Yen-Long Lee, Soon-Jyh Chang:
A quick jitter tolerance estimation technique for bang-bang CDRs. 8-13 - Mehmet Ince, Ender Yilmaz, Jae Woong Jeong, LeRoy Winemberg, Sule Ozev:
Evaluation of loop transfer function based dynamic testing of LDOs. 14-19 - Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy:
Test generation for open and delay faults in CMOS circuits. 21-26 - Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen:
Cell-aware test generation time reduction by using switch-level ATPG. 27-32 - Matthew Beckler, R. D. Shawn Blanton:
GPU-accelerated fault dictionary generation for the TRAX fault model. 34-39 - Po-Hao Chen, Chi-Lin Lee, Jing-Yu Chen, Po-Wei Chen, James Chien-Mo Li:
Physical-aware diagnosis of multiple interconnect defects. 40-45 - Shuo-Lian Hong, Kuen-Jong Lee:
A run-pause-resume silicon debug technique for multiple clock domain systems. 46-51 - Chih-Hao Wang, Tong-Yu Hsieh:
A hybrid concurrent error detection scheme for simultaneous improvement on probability of detection and diagnosability. 52-57 - Andreina Zambrano, Hans G. Kerkhoff:
A dependable AMR sensor system for automotive applications. 59-64 - Hans G. Kerkhoff, Ghazanfar Ali, Hassan Ebrahimi, Ahmed Ibrahim:
An automotive MP-SoC featuring an advanced embedded instrument infrastructure for high dependability. 65-70 - Cheng-Wen Wu, Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen:
Symbiotic system models for efficient IGT system design and test. 71-76 - Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen:
A lightweight X-masking scheme for IoT designs. 77-82 - Hao Chen, Hung-Chih Lin, Min-Jer Wang:
Fan-out wafer level chip scale package testing. 84-89 - Tang-Jung Chiu, Yu-Lun Tseng, Yen-Cheng Lin, Yi-Chen Wang, Hung-Chih Lin, Min-Jer Wang:
Testing-for-manufacturing (TFM) for ultra-thin IPD on InFO. 90-95 - Abhishek Bhattacharya, Ramesh Tekumalla:
Test strategy for storage SOCs. 96-99 - Shyue-Kung Lu, Hung-Kai Huang:
Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh power. 101-106 - Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. 107-111 - Jais Abraham, Uttam Garg, Glenn Colón-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, Martin Keim:
Adapting an industrial memory BIST solution for testing CAMs. 112-117 - Michael A. Kochte, Rafal Baranowski, Hans-Joachim Wunderlich:
Trustworthy reconfigurable access to on-chip infrastructure. 119-124 - Yousuke Miyake, Yasuo Sato, Seiji Kajihara:
On the effects of real time and contiguous measurement with a digital temperature and voltage sensor. 125-130 - Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur:
Enhancing security of logic encryption using embedded key generation unit. 131-136 - Davide Appello, M. Laurino, Marco Pranzo:
A mathematical model to assess the influence of parallelism in a semiconductor back-end test floor. 138-143 - Erik Jan Marinissen, Ferenc Fodor, Bart De Wachter, Jorg Kiesewetter, Eric Hill, Ken Smith:
A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards. 144-149 - Young-Woo Lee, Inhyuk Choi, Kang-Hoon Oh, James Jinsoo Ko, Sungho Kang:
Test item priority estimation for high parallel test efficiency under ATE debug time constraints. 150-154 - Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue:
State assignment for fault tolerant stochastic computing with linear finite state machines. 156-161 - Yi-Ju Ke, Yi-Chieh Ghen, Jng-Jer Huang:
An integrated design environment of fault tolerant processors with flexible HW/SW solutions for versatile performance/cost/coverage tradeoffs. 162-167 - Charles Chia-Hao Hsu, Charles H.-P. Wen:
Speeding up power verification by merging equivalent power domains in RTL design with UPF. 168-173
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