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ORCIDITC 1995: Washington, DC, USA
- Proceedings IEEE International Test Conference 1995, Driving Down the Cost of Test, Washington, DC, USA, October 21-25, 1995. IEEE Computer Society 1995, ISBN 0-7803-2992-9
Session 1: Plenary
Keynote Address
- Kenneth M. Thompson:
Intel and the Myths of Test. ITC 1995: 10
Invited Address
- Philippe Chauveau:
Design and Testing of the On-Ramps to the Information Superhighway. ITC 1995: 11
Session 2: RAM BIST and Intelligent Testing
- O. Kebichi, Michael Nicolaidis, Vyacheslav N. Yarmolik:
Exact Aliasing Computation for RAM BIST. 13-22 - Bruce F. Cockburn, Y.-F. Nicole Sat:
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs. 23-32 - Luigi Ternullo Jr., R. Dean Adams, John Connor, Garret S. Koch:
Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor Subsystem. 33-44 - Th. Calin, F. L. Vargas, Michael Nicolaidis:
Upset-Tolerant CMOS SRAM Using Current Monitoring: Prototype and Test Experiments. 45-53
Session 3: New Test Considerations for Mixed-Signal Devices
- Peter D. Capofreddi, Bruce A. Wooley:
The Use of Linear Models for the Efficient and Accurate Testing of A/D Converters. 54-60 - Manoj Sachdev, Bert Atzema:
Industrial Relevance of Analog IFA: A Fact or a Fiction. 61-70 - Yukiya Miura:
A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent Testing. 71-77 - Xavier Haurie, Gordon W. Roberts:
Arbitrary-Precision Signal Generation for Bandlimited Mixed-Signal Testing. 78-86
Session 4: Quality, I-DDQ, and the DUT Interface
- Solomon Max:
Visualizing Quality. 87-96 - Gerald H. Johnson, Jan B. Wilstrup:
A General Purpose ATE Based IDDQ Measurement Circuit. 97-105 - Karl F. Zimmermann:
SiPROBE - A New Technology for Wafer Probing. 106-112
Session 5: Delay Testing
- Ira Pramanick, Ankan K. Pramanick:
Parallel Delay Fault Coverage and Test Quality Evaluation. 113-122 - Alicja Pierzynska, Slawomir Pilarski:
Non-Robust versus Robust. 123-131 - Mukund Sivaraman, Andrzej J. Strojwas:
Test Vector Generation for Parametric Path Delay Faults. 132-138 - Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. 139-148
Session 6: Microprocessor Test
- Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell:
Test Generation and Design for Test for a Large Multiprocessing DSP. 149-156 - Marc E. Levitt, Srinivas Nori, Sridhar Narayanan, G. P. Grewal, Lynn Youngs, Anjali Jones, Greg Billus, Siva Paramanandam:
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor. 157-166 - Jen-Tien Yen, Marie Sullivan, Carlos Montemayor, Pete Wilson, Richard Evers:
Overview of PowerPCTM 620 Multiprocessor Verification Strategy. 167-174 - Hong Hao, Rick Avra:
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation. 175-183
Session 7: MCM Test Methods
- Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan, David E. Schimmel:
A Novel Low-Cost Approach to MCM Interconnect Test. 184-192 - Kevin T. Kornegay, Kaushik Roy:
Integrated Test Solutions and Test Economics for MCMs. 193-201 - Andrew Flint:
A Comparison of Test Requirements, Methods, and Results for Seven MCM Products. 202-207 - Koppolu Sasidhar, Abhijit Chatterjee, Vinod K. Agarwal, Joseph L. A. Hughes:
Distributed Probabilistic Diagnosis of MCMs on Large Area. 208-216
Session 8: Test SPC and Support Systems
- James A. Tuttle, Thomas W. Collins, Mary Stone Tuttle:
Matching Models to Real Life for Defect Reduction. 217-223 - Willie Benitez, Deo Marrero, Douglas J. Mirizzi, Dale Ohmart:
Test SPC: A Process to Improve Test System Integrity. 224-232 - Alex M. Ijaz, Eugene R. Hnatek:
User Application of Statistical Process Monitor Techniques to ASIC Critical Parameters. 233-241 - Susan D. Shaye:
A Test Data Collection System for Uniform Data Analysis. 242-251
Session 9: Test Generation and Fault Simulation
- Jos van Sas, Erik Huyskens, Hans Naert, Fred Schell, Ad J. van de Goor:
Coping with Re-usability Using Sequential ATPG: A Practical Case Study. 252-261 - Ben Mathew, Daniel G. Saab:
DFT & ATPG: Together Again. 262-271 - Irith Pomeranz, Sudhakar M. Reddy:
Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach. 272-281 - Stefan Weiner:
A Fault Model and a Test Method for Analog Fuzzy Logic Circuits. 282-291
Session 10 - Panel: Designers are from Venus, Test Engineers are from Mars
- Thomas L. Anderson:
A Designer's View of Chip Test. 292
Session 11 - Panel: Is High-Level Test Synthesis just DFT?
- Rabindra K. Roy:
Advantages of High-Level Test Synthesis over Design for Test. 293 - Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre:
Is High-Level Test Synthesis Just Design for Test? 294 - Peter C. Maxwell:
The Many Faces of Test Synthesis. 295
Session 12 - Panel: Test Challenges of Contract Manufacturing
- Randall Hassig:
The Case for Contract Manufacturing. 296 - Tom Langford:
Contract Manufacturing: How Much Can They Do? 297
Session 13 - Panel: Why is Mixed-Signal Testing Such a Mess Anyway?
- Gordon W. Roberts:
Re-examining the Needs of the Mixed-Signal Test. 298
Session 14 - Panel: Test Quality: Stuck-at Fault, PPM Rejects or?
- Keith Baker:
Stuck-at Faults, PPMs Rejects or? What doe the SIA Roadmaps Say? 299 - John M. Acken:
The Final Barriers to Widespread Use of IDDQ Testing. 300 - Ron Wantuck:
Test Quality: Required Stuck-at Fault Coverage with the Use of IDDQ Testing. 301
Session 15: Design for Testability - I
- Vishwani D. Agrawal, Tapan J. Chakraborty:
High-Performance Circuit Testing with Slow-Speed Testers. 302-310 - Stephen Pateras, Martin S. Schmookler:
Avoiding Unknown States When Scanning Mutually Exclusive Latches. 311-318 - Richard M. Sedmak, John Evans:
A Hierarchical, Desgin-for-Testability (DFT) Methodology for the Rapid Prototyping of Application-Specific Signal Processors (RASSP). 319-327
Session 16: IC Test Issues
- A. Frisch, Mitch Aigner, T. Almy, Hans J. Greub, Mousumi Mitra Hazra, S. Mohr, Nicholas J. Naclerio, W. Russell, M. Stebniskey:
Supplying Known-Good Die for MCM Applications Using Low-Cost Embedded Testing. 328-335 - V. Ramakrishnan, D. M. H. Walker:
IC Performance Prediction System. 336-344 - Fabian Vargas, Michael Nicolaidis, Yervant Zorian:
An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring. 345-354
Session 17: New Test Techniques for Mixed-Signal Devices
- Mark Burns:
Improving DSP-Based Measurements with Spectral Interpolation. 355-363 - Luke S. L. Hsieh, Andrew Grochowski:
THD and SNR Tests Using the Simplified Volterra Series with Adaptive Algorithms. 364-369 - Harold Bogard, Celeste Repasky:
Increasing Test Throughput Through the Implementation of Parallel Test on a 16-Bit Multimedia Audio CODEC. 370-376
Session 18: Microprocessor-Related Topics
- Junichi Hirase:
Improvement of the Defect Level of Micro-computer LSI Testing. 377-383 - Janusz Sosnowski
:
In-System Testing of Cache Memories. 384-393 - Laurence Goodby, Alex Orailoglu:
Towards 100% Testable FIR Digital Filters. 394-402
Session 19: Design for Testability - II
- Xinli Gu, Krzysztof Kuchcinski, Zebo Peng:
An Efficient and Economic Partitioning Approach for Testability. 403-412 - Insung Park, Dong Sam Ha, Gyoochan Sim:
A New Method for Partial Scan Design Based on Propagation and Justification Requirements of Faults. 413-422 - Prashant S. Parikh, Miron Abramovici:
On Combining Design for Testability Techniques. 423-429
Session 20: Applications of Test Cost Analysis
- Chryssa Dislis, A. F. Al-Ani, Ian P. Jalowiecki:
MCM Quality and Cost Analysis Using Economics Models. 430-437 - Junichi Hirase:
Study on the Costs of On-site VLSI Testing. 438-443 - Stephen K. Sunter:
The P1149.4 Mixed Signal Test Bus: Costs and Benefits. 444-450
Session 21: High-Speed ATE Architectures and Timing
- Shuji Kikuchi, Yoshihiko Hayashi, Takashi Suga, Jun Saitou, Masahiko Kaneko, Takashi Matsumoto, Ryozou Yoshino:
A Gate-Array-Based 666MHz VLSI Test System. 451-458 - Jim Chapman, Jeff Currin, Steve Payne:
A Low-Cost High-Performance CMOS Timing Vernier for ATE. 459-468 - Michael G. Davis:
Evaluating Waveform-Generation Capabilities of VLSI Test Systems. 469-478
Session 22: Defect Detection and Diagnosis
- Adit D. Singh, Haroon Rasheed, Walter W. Weber:
IDDQ Testing of CMOS Opens: An Experimental Study. 479-489 - Gregory A. Maston:
Production IDDQ Testing with Passive Current Compensation. 490-497 - Robert C. Aitken:
Finding Defects with Fault Models. 498-505
Session 23: Performance-Driven BIST Insertion
- Kwang-Ting Cheng, Chih-Jen Lin:
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST. 506-514 - Claus Schotten, Heinrich Meyr:
Test Point Insertion for an Area Efficient BIST. 515-523 - Charles Njinda, Neeraj Kaul:
Performance Driven BIST Technique for Random Logic. 524-533
Session 24: IC-Defect Detection: Advancements in Design, Test and Analysis Methods
- Manoj Sachdev:
IDDQ and Voltage Testable CMOS Flip-flop Configurations. 534-543 - Jaume Segura, Carol de Benito, Antonio Rubio, Charles F. Hawkins:
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level. 544-551 - Jitendra Khare, Wojciech Maly:
Inductive Contamination Analysis (ICA) with SRAM Application. 552-560
Session 25: Uniformity and Flexibility: Capatalizing on Boundary-Scan's Assets
- Douglas W. Raymond, D. Eugene Wedge, Philip J. Stringer, Harold W. Ng, Suzanne T. Jennings, Craig T. Pynn, Winsor Soule Jr.:
Algorithmic Extraction of BSDL from 1149.1-compliant Sample ICs. 561-568 - David J. Cheek, Ramaswami Dandapani:
Integration of IEEE Std. 1149.1 and Mixed-Signal Test Architectures. 569-576 - Douglas Reed, Jason Doege, Antonio Rubio:
Improving Board and System Test: A Proposal to Integrate Boundary Scan and IDDQ. 577-585
Session 26: Test at the Functional Level
- Mark C. Hansen, John P. Hayes:
High-Level Test Generation Using Symbolic Scheduling. 586-595 - Mark Kassab, Janusz Rajski, Jerzy Tyszer:
Hierarchical Functional-Fault Simulation for High-Level Synthesis. 596-605 - Samy Makar, Edward J. McCluskey:
Functional Tests for Scan Chain Latches. 606-615
Session 27: IC Testing and Diagnosis
- Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
On Efficiently and Reliably Achieving Low Defective Part Levels. 616-625 - Young-Jun Kwon, D. M. H. Walker:
Yiel Learning via Functional Test Data. 626-635 - Kaushik De, Arun Gunda:
Failure Analysis for Full-Scan Circuits. 636-645
Session 28: Topics in Test Techniques
- Michael K. Williams:
A Discussion of Methods for Measuring Low-Amplitude Jitter. 646-652 - Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey:
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design. 653-662 - Siyad C. Ma, Piero Franco, Edward J. McCluskey:
An Experimental Chip to Evaluate Test Techniques: Experiment Results. 663-672
Session 29 - Case Studies: Successful Experiences with MCM Test
- Andrew Flint:
Using the Right Tools and Techniques leads to Successful Testing of MCMs. 673
Session 30: Synthesis for Testability
- Nur A. Touba, Edward J. McCluskey:
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. 674-682 - Samir Lejmi, Bozena Kaminska, Bechir Ayari:
Synthesis and Retiming for the Pseudo-Exhaustive BIST of Synchronous Sequential Circuits. 683-692 - Christos A. Papachristou, Joan Carletta:
Test Synthesis in the Behavioral Domain. 693-702
Session 31: Software Testing
- Roger Ferguson, Bogdan Korel:
Software Test Data Generation Using the Chaining Approach. 703-709 - Yves Le Traon, Chantal Robach:
From Hardware to Software Testability. 710-719 - Charles Anderson, Anneliese von Mayrhauser, Richard T. Mraz:
On the Use of Neural Networks to Guide Software Testing Activities. 720-729 - John C. Munson, Gregory A. Hall:
Dynamic Program Complexity and Software Testing. 730-737
Session 32 - Case Studies: Test Synthesis
- Kamalesh N. Ruparel:
Test Synthesis: From Wishful Thinking to Reality. 738
Session 33: Unconventional Test Development
- Keith Baker, T. F. Waayers, F. G. M. Bouwman, M. J. W. Verstraelen:
Plug & Play IDDQ Monitoring with QTAG. 739-749 - Birger Schneider, Soeren Soegaard:
IntegraTEST: The New Wave in Mixed-Signal Test. 750-760 - Jean Qincui Xia, Tom Austin, Nash Khouzam:
Dynamic Test Emulation for EDA-Based Mixed-Signal Test Development Automation. 761-770 - Scot Bullock:
Report on a Pilot Project Successfully Implementing a Design-to-Test Methodology. 771-780
Session 34: Systems and Testing: Practical Applications and Costs
- Chouki Aktouf, Chantal Robach, A. Marinescu:
A Routing Testing of a VLSI Massively Parallel Machine Based on IEEE 1149.1. 781-788 - Wuudiann Ke, Duy Le, Najmi T. Jarwala:
A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus. 789-796 - Rodham E. Tulloss:
Leave the Wires to Last - Funcitonal Evaluation of the IEEE Std 1149.5 Module Test and Maintenance Bus. 797-806 - Des Farren, Anthony P. Ambler:
Cost-Effective System-Level Test Strategies. 807-813
Session 35: BIST Pattern Generation and Compaction
- Chih-Ang Chen, Sandeep K. Gupta:
A Methodology to Design Efficient BIST Test Pattern Generators. 814-823 - Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
An Effective BIST Scheme for Booth Multipliers. 824-833 - Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes:
Optimal Space Compaction of Test Responses. 834-843
Session 36: Design and Simulations Topics
- Carol Pyron, William C. Bruce:
Implementing 1149.1 in the PowerPCTM RISC Microprocessor Family. 844-850 - Lee Whetsel:
Improved Boundary Scan Design. 851-860 - Kamal K. Varma:
Compiled Code, Dynamic Worst Case Timing Simulation Tracking Multiple Causality. 861-869
Session 37: Changing the Test Paradigm: ATE and Board Test Systems
- Ulrich Schoettmer, Toshiyuki Minami:
Challenging the "High Performance - High Cost" Paradigm in Test. 870-879 - Garry C. Gillette:
A Single Board Test System: Changing the Test Paradigm. 880-885 - Gary J. Lesmeister:
A Tester for DesignTM (TFD). 886-891
Session 38: IC Current-Test Techniques, Production Results, and Quality Improvement Methods
- Rafic Z. Makki, Shyang-Tai Su, H. Troy Nagle:
Transient Power Supply Current Testing of Digital CMOS Circuits. 892-901 - Hitesh Ahuja, Dean Arriens, Ben Schneller, Vandana Verma, Wendy Whitman:
Intel 386TM EX Embedded Processor IDDQ Testing. 902-909 - Kenneth M. Wallquist:
On the Effect of ISSQ Testing in Reducing Early Failure Rate. 910-915
Session 39 - Panel: Highlights of the MCM Test Workshop
- Alan W. Righter:
Solving Known Good Die (and Substrate) Test Issues. 916 - David C. Keezer:
Electrical Troubleshooting, Diagnostics, and Repair of Multichip Modules. 917
Session 40 - Panel: What New Test Standards Do We Need?
- Lawrence D. Carpenter:
Required - A Portable Test Standard. 918 - Gregory A. Maston:
STIL from the Users Perspective. 919
Session 41 - Panel: Bringing Down the Cost of Test... The ATE Way?... The DFT Way?... The Boundary Scan Way?... The I-DDQ Way?... Or What?
- Gary O'Donnell:
It's DFT, Boundary Scan and Life Cycle Benefits. 920 - William R. Simpson:
Cutting the Cost of Test; the Value-added Way. 921 - Prab Varma:
Optimizing Product Profitability - The Test Way. 922
Session 42 - Panel: What's so Different about Deep-Submicron Test?
- Kenneth M. Butler:
Deep Submicron: Is Test Up to the Challenge? 923 - Craig Hunter:
What's So Different about Deep-Submicron Test? 924
ITC Lecture Series: Unpowered "Opens" Testing
- Kenneth P. Parker, David Greene:
The ITC Lecture Series: An Experiment. 925 - Jack Ferguson:
Finding I/O Faults on In-Circuit ICs Using Parasitic Transistor Tests. 926 - Joe Wrinn:
Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test & Radio Frequency Induction Test. 927 - Ted T. Turner:
Capacitive Leadframe Testing. 928
Session T1: Telecom Test: The Future is Here!
- James Jamieson:
Telecom Test: New Challenges, Old Roots. 929
Session T2: Design-For-Test Strategies for Novel Telecommunications Test Problems
- Benoît R. Veillette, Gordon W. Roberts:
A Bulti-in Self-Test Strategy for Wireless Communication Systems. 930-939 - Madhuri Jarwala, Duy Le, Michael S. Heutmaker:
End-to-End Test Strategy for Wireless Systems. 940-946 - Stefano Barbagallo, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Testing a Switching Memory in a Telcommunication System. 947-956
Session T3: Test Technology and Strategy Challenges Facing Telecom Manufacturing Test
- Rob Tepper, Jim Tarpo:
Automated 1.5 GHz Sonet Characterization. 957-965 - Michael T. Freeman:
Development of an ATE Test Station for Mixed CATV/TELCO Products. 966-972 - Mark Hoogerbrugge:
Optimizing Test Strategies for SONET/SDH/ATM Network Element Manufacturing. 973-978
Session T4: Telecom Systems: Are We Getting What We Wanted?
- Martin A. Schulman:
End-to-End Performance Measurement for Interactive Multimedia Television. 979-985 - Harry Hulvershorn, Paul Soong, Saman Adham:
Linking Diagnostic Software to Hardware Self Test in Telecom Systems. 986-993 - Benoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham:
A New Hardware Fault Insertion Scheme for System Diagnostics Verification. 994-1002
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