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ORCIDVLSI-DAT 2022: Hsinchu, Taiwan
- 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022, Hsinchu, Taiwan, April 18-21, 2022. IEEE 2022, ISBN 978-1-6654-0921-6
- Sying-Jyan Wang
, Yen-Chang Shih, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong:
Improving IJTAG Test Efficiency and Security. 1-4 - Zahra Heshmatpour, Lihong Zhang, Howard M. Heys:
Robust CNFET Circuit Sizing Optimization. 1-4 - M. P. Pavan Kumar, Cheng-Jyun Tang, Kun-Chih Jimmy Chen:
Composite Fault Diagnosis of Rotating Machinery With Collaborative Learning. 1-4 - Yen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu:
An Injection-Locked Clock Multiplier With Injection Strength Calibration. 1-4 - Chong-Yin Lu, Ren-Song Tsay, Weyshin Chang:
An Embedded CNN Design for Edge Devices Based on Logarithmic Computing. 1-4 - Mike Shuo-Wei Chen:
Non-Uniform Sampling Data Converters: A Journey to Uncharted Circuits and Systems. 1 - Yun-Shiang Shu:
Introduction of Noise-Shaping SAR ADCs. 1 - Wan-Ting Chang, Chih-Hung Kuo, Li-Chun Fang:
Variational Channel Distribution Pruning and Mixed-Precision Quantization for Neural Network Model Compression. 1-3 - Hong-Hao Wang, Po-Yao Chuang, Cheng-Wen Wu:
A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime. 1-4 - Yi-Da Hsin, Yen-Shi Kuo, Bo-Cheng Lai:
Distributed Sorting Architecture on Multiple FPGA. 1-4 - Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou:
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. 1-4 - Kung-Yen Lee:
The Applications of SiC Power Devices in Renewable Energy and EV. 1 - Pai-Yu Tan, Chih-Hsuan Tung, Cheng-Wen Wu, Mincent Lee, Gordon Liao:
A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array. 1-4 - Jen-Wei Liang:
Practical Considerations of In-Memory Computing in the Deep Learning Accelerator Applications. 1 - Shien-Chun Luo, Kuo-Chiang Chang, Po-Wei Chen, Zhao-Hong Chen:
Configurable Deep Learning Accelerator with Bitwise-accurate Training and Verification. 1-4 - Shao-Yu Shu, Chun-Hung Lin, Ching-Yuan Yang:
A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion. 1-4 - Tung-Yi Chan:
Challenges and Opportunities in Building Secure IoT Platforms. 1 - Yi-Chieh Kao, Hung-An Chen, Hsi-Pin Ma:
An FPGA-Based High-Frequency Trading System for 10 Gigabit Ethernet with a Latency of 433 ns. 1-4 - Zhi-Heng Kang, Yu-Chi Yen, Guan-Yu Su, Shen-Iuan Liu:
An Adaptive Digital PLL Based on BBPFD Transition Probability. 1-4 - Kushagra Agarwal, Aryamaan Jain, Deepthi Amuru, Zia Abbas:
Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits. 1-4 - Massimo Alioto:
Circuits and Architectures for Next-generation Attentive & Intelligent Systems. 1 - Vincent Hsu:
2.5D & 3DIC Advanced Packaging: An EDA Perspective. 1-2 - Yuji Yano, Hisashi Iwamoto, Takuma Yoshimura, Yoshihiro Nishida, Tatsuya Mori, Kiyotaka Komoku, Hidekuni Takao, Kazutami Arimoto:
28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System. 1-4 - Yen-Po Lai, Hao-Hsuan Chang, Tai-Cheng Lee:
An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter. 1-4 - Zong-Hua Tsai, Aaron C.-W. Liang, Charles H.-P. Wen:
SlewFTA: Functional Timing Analysis Considering Slew Propagation. 1-4 - Youbiao He, Hebi Li, Jin Tian, Forrest Sheng Bao:
Circuit Routing Using Monte Carlo Tree Search and Deep Reinforcement Learning. 1-5 - Che-Chang Yang, Yung-Tai Shih, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu:
Efficient Segment-wise Pruning for DCNN Inference Accelerators. 1-4 - Ming-Nan Cheng:
AIoT Security - from the Perspective of a Microcontroller. 1 - Xingyu Wang, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang, Hirofumi Shinohara:
A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement. 1-4 - Meng-Yi Wu:
Hardware Root-of-Trust Design Based on on-chip PUF for AIoT Applications. 1 - Takekazu Tabata:
A64FX: 52 Core Processor Designed for the Supercomputer Fugak. 1 - Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen:
Substrate Signal Routing Solution Exploration for High-Density Packages with Machine Learning. 1-4 - Akhilesh Kumar, Norman Chang, David Geb, Haiyang He, Stephen H. Pan, Jimin Wen, Saeed Asgari, Mehdi Abarham, Chris Ortiz:
ML-based Fast On-Chip Transient Thermal Simulation for Heterogeneous 2.5D/3D IC Designs. 1-8 - I-Hsuan Wu, Ming-Dou Ker:
Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control. 1-4 - TaiKang Shing:
Wide Band Gap Devices for Power System. 1-2 - Ching-Che Chung, Yi-Ting Tsai:
A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes. 1-4 - L. C. Lu:
Semiconductor Evolution for Chip and System Design- From 2D Scaling to 3D Heterogeneous Integration. 1 - Wei-Cheng Chou, Cheng-Wei Huang, Juinn-Dar Huang:
Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets. 1-4 - Youngcheol Chae:
Low-power Continuous-time Delta-sigma ADCs. 1 - K. Lawrence Loh:
Technology Challenges to IC Industry for Next Decade. 1 - Yoojin Ban:
Silicon Photonics for Scaling the Cloud and Enabling AI. 1 - Pen-Jui Peng:
Design of ultra-high-speed Transmitters Beyond 100Gb/s in CMOS Technology. 1 - Boris Murmann:
Bridging the Physical and Digital Worlds in Data-Driven Systems. 1 - Ming-Wei Lin:
A Silicon Photonics Technology for 400 Gbit/s Applications. 1 - Chih-Wen Huang:
Product level design considerations and solutions for RF GaN applications. 1-2 - Kang-Yi Fan, Jyun-Hua Chen, Chien-Nan Liu, Juinn-Dar Huang:
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. 1-4 - Mitsuhisa Sato:
The Supercomputer "Fugaku". 1 - Chen-Yi Lee:
Bio-Chips for Fast Medial Tests Networks. 1 - Taisuke Boku:
How FPGA can contribute to HPC ? 1
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