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ORCIDVTS 2005: Palm Springs, CA, USA
- 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA. IEEE Computer Society 2005, ISBN 0-7695-2314-5
Introduction
- Foreword.
- Organizing Committee.
- Steering Committee.
- Program Committee.
- Reviewers.
- Acknowledgments.
- Test Technology Technical Council.
- Test Technology Educational Program: Overview of Tutorials.
Plenary Session
- VTS 2004 Best Paper Award.
- VTS 2004 Best Panel Award.
- VTS 2004 Best Innovative Practices Session Award.
1A: Memory BIST
- Dilip K. Bhavsar:
A Built-in Self-Test Method for Write-only Content Addressable Memories. 9-14 - Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu
, Chien-Hung Ho, Yen-Tai Lin:
Flash Memory Built-In Self-Diagnosis with Test Mode Control. 15-20 - Ismet Bayraktaroglu, Olivier Caty, Yickkei Wong:
Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories. 21-26
1B: Delay Testing I
- Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee:
Transition Tests for High Performance Microprocessors. 29-34 - Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak:
On Silicon-Based Speed Path Identification. 35-41 - Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic:
At-Speed Transition Fault Testing With Low Speed Scan Enable. 42-47
1C: IP Session - Multisite Testing
2A: Memory Testing I
- Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March Tests for Unlinked Static Faults in Random Access Memories. 53-59 - Jin-Fu Li, Chou-Kun Lin:
Modeling and Testing Comparison Faults for Ternary Content Addressable Memories. 60-65 - Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian:
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. 66-71
2B: High-Speed Testing and Clock Skew Compensation
- Darren Aaberge, Ken Mockler, Dieu Van Dinh, Raoul Belleau, Tim Donovan, Reid Hewlitt:
Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities. 75-84 - Hitoshi Iwai, Atsushi Nakayama, Naoko Itoga, Kotaro Omata:
Cantilever Type Probe Card for At-Speed Memory Test on Wafer. 85-89 - Martin Omaña, Daniele Rossi, Cecilia Metra:
Low Cost Scheme for On-Line Clock Skew Compensation. 90-95
2C: IP Session - DFT for SoCs in Wireless Applications
3A: Test Data Compression and Self-Test
- Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel:
Implementing a Scheme for External Deterministic Self-Test. 101-106 - Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen:
On A Software-Based Self-Test Methodology and Its Application. 107-113 - Janusz Rajski, Jerzy Tyszer:
Synthesis of X-Tolerant Convolutional Compactors. 114-119
3B: Analog Testing I
- Dongwoo Hong, Cameron Dryden, Gordon Saksena:
An Efficient Random Jitter Measurement Technique Using Fast Comparator Sampling. 123-130 - Anup P. Jose, Keith A. Jenkins, Scott K. Reynolds:
On-Chip Spectrum Analyzer for Analog Built-In Self Test. 131-136 - Soumendu Bhattacharya, Abhijit Chatterjee:
Production Test Methods for Measuring 'Out-of-Band' Interference of Ultra Wide Band (UWB) Devices. 137-142
3C: IP Session - Soft Errors
4A: Defect-Oriented Testing
- Scott Davidson:
Towards an Understanding of No Trouble Found Devices. 147-152 - Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir:
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. 153-160 - Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey:
Effective TARO Pattern Generation. 161-166
4B: IP Session - Adaptive Test
4C: IP Session - High Speed I/O Test
5A: Panel Session - Robust Design from Unreliable Components: Why? When? How?
5B: Emerging Technologies - Reliable and Fault-Tolerant Wireless Sensor Networks
6A: Memory Testing II
- Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg:
A New Algorithm for Dynamic Faults Detection in RAMs. 177-182 - Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan:
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. 183-188 - John C. Koob, Sue Ann Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler L. Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott:
Test and Characterization of a Variable-Capacity Multilevel DRAM. 189-197
6B: FPGA & MEMS Testing
- Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu:
A BIST Scheme for FPGA Interconnect Delay Faults. 201-206 - Ghazanfar Asadi, Mehdi Baradaran Tahoori:
Soft Error Mitigation for SRAM-Based FPGAs. 207-212 - Norbert Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet:
On-Chip Electro-Thermal Stimulus Generation for a MEMS-Based Magnetic Field Sensor. 213-218
6C: IP Session - IP in Wireless Testing
7A: Delay Testing II
- Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press:
Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. 223-228 - Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng:
Pseudo-Functional Scan-based BIST for Delay Fault. 229-234 - Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker:
Static Compaction of Delay Tests Considering Power Supply Noise. 235-240
7B: RF Testing
- Selim Sermet Akbay, Abhijit Chatterjee:
Built-In Test of RF Components Using Mapped Feature Extraction Sensors. 243-248 - Alberto Valdes-Garcia, Radhika Venkatasubramanian, Rangakrishnan Srinivasan, José Silva-Martínez, Edgar Sánchez-Sinencio:
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers. 249-254 - Achintya Halder, Abhijit Chatterjee:
Low-Cost Alternate EVM Test for Wireless Receiver Systems. 255-260
7C: IP Session: Embedded Memory Test & Repair Drives Higher Yield in Nanometer Technologies
8A: Low-Power Testing
- Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
On Low-Capture-Power Test Generation for Scan Testing. 265-270 - Kirti Joshi, Eric W. MacDonald:
Reduction of Instantaneous Power by Ripple Scan Clocking. 271-276 - Min-Hao Chiu, Chien-Mo James Li:
Jump Scan: A DFT Technique for Low Power Testing. 277-282
8B: Nanometer and Circuit-Level Effects
- Cameron Dryden:
Survey of Design and Process Failure Modes for High-Speed SerDes in Nanometer CMOS. 285-291 - Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy:
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. 292-297 - Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. 298-303
8C: IP Session - Test Resource Partitioning in Action
9A: Embedded Tutorial: Test with Variations - How Much Can Be Solved in the Design Process?
9C: Panel Session - Are DFT and Manufacturing Test Good Boosts for DFM?
10A: Reliability
- Shalini Ghosh, Sugato Basu, Nur A. Touba:
Synthesis of Low Power CED Circuits Based on Parity Codes. 315-320 - Fei Su, Krishnendu Chakrabarty:
Defect Tolerance for Gracefully-Degradable Microfluidics-Based Biochips. 321-326 - Kartik Mohanram:
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design. 327-333
10B: Testing of Bridging Faults and Test Scheduling
- Sreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee:
Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor. 337-342 - Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker:
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. 343-348 - Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota:
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. 349-354
10C: IP Session - SoC Test Practices in Japan
11A: Diagnosis
- Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew:
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. 359-365 - Rao Desineni, R. D. (Shawn) Blanton:
Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction. 366-373 - Erkan Acar, Sule Ozev:
Diagnosis of Failing Component in RF Receivers through Adaptive Full-Path Measurements. 374-379
11B: Analog Testing II
- Yun-Che Wen:
A BIST Scheme for Testing Analog-to-Digital Converters with Digital Response Analyses. 383-388 - Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell:
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. 389-394 - Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
Constructive Derivation of Analog Specification Test Criteria. 395-400
11C: IP Session - Delay Fault Testing: Industrial Case Studies
12A: Design-for-Testability
- Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuck:
Segmented Addressable Scan Architecture. 405-411 - Yu-Ting Lin, Tony Ambler:
An Economic Selecting Model for DFT Strategies. 412-417 - Loganathan Lingappan, Niraj K. Jha:
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. 418-423
12B: I_DDQ Testing and Power Supply Noise Analysis
- Ritesh P. Turakhia, Brady Benware, Robert Madge, Thaddeus T. Shannon, W. Robert Daasch:
Defect Screening Using Independent Component Analysis on I_DDQ. 427-432 - Dhruva Acharyya, Jim Plusquellic:
Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. 433-438 - Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed:
Pattern Generation and Estimation for Power Supply Noise Analysis. 439-444
12C: IP Session - On the Way from DFT to DFM...Looking for Systematic Marginalities
13A: Panel Session - IEEE 1500: Embedded Core-Based Test Standard: Why Should I Adopt It?
13B: Hot Topic Session - Test and DFM: Managing Yield at 90nm and below
13C: Panel Session - Analog TRP: Is Convergence on Horizon?
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