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ORCID43rd VTS 2025: Tempe, AZ, USA
- 43rd IEEE VLSI Test Symposium, VTS 2025, Tempe, AZ, USA, April 28-30, 2025. IEEE 2025, ISBN 979-8-3315-2144-8
- Peter Domanski, Mukarram Ali Faridi, Gabriel Kaunang, Wilson Pradeep, Adit D. Singh, Muhammad Alfian Amrizal, Yanjing Li, Farshad Firouzi, Krishnendu Chakrabarty:
Silent Data Corruption: Advancing Detection, Diagnosis, and Mitigation Strategies. 1-11 - Jeng-Yu Liao, Li-Yang Wang, James Chien-Mo Li, Harry H. Chen:
Multi-core Vmin and Worst-core Vmin Prediction using SOMAC. 1-7 - Mahboobe Sadeghipour Roodsari, Vincent Meyers, Mehdi B. Tahoori:
CED-HDC: Lightweight Concurrent Error Detection for Reliable Hyperdimensional Computing. 1-7 - Haocong Luo, Ismail Emir Yüksel, Ataberk Olgun, A. Giray Yaglikçi, Onur Mutlu:
Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies. 1-8 - Nelson M.-C. Wu, Lowry P.-T. Wang, Chia-Wei Liang, Charles H.-P. Wen, Herming Chiueh:
Designing Radiation-Hardened D Flip-Flop with Reduced Latency and Area Using Filtering Buffer. 1-7 - Tanzim Mahfuz, Pravin Gaikwad, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty:
SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection. 1-7 - Devashri Naik, Nastaran Darabi, Sina Tayebati, Dinithi Jayasuriya, Shamma Nasrin, Danush Shekar, Corrinne Mills, Benjamin Parpillon, Farah Fahim, Mark S. Neubauer, Amit Ranjan Trivedi:
From Signals to Features to Insights: Multi-Level Novelty Detection for Fast Scientific Discovery. 1-4 - Sumukh Prashant Bhanushali, Shamma Nasrin, Debnath Maiti, Arindam Sanyal:
Machine-learning based Blind Digital Calibration of Time-Interleaved ADC. 1-5 - Mohammad Hashemi, Shahin Tajik, Fatemeh Ganji:
Garblet: Multi-party Computation for Protecting Chiplet-based Systems. 1-7 - Yuxuan Yin, Rebecca Chen, Chen He, Peng Li:
Data-Efficient Prediction of Minimum Operating Voltage via Inter- and Intra-Wafer Variation Alignment. 1-7 - Dinesh Reddy Ankireddy, Sudipta Paria
, Aritra Dasgupta, Sandip Ray, Swarup Bhunia:
CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking. 1-7 - Francesco Angione, Paolo Bernardi, Alberto Bosio, Harish Dattatraya Dixit, Salvatore Pappalardo, Annachiara Ruospo, Ernesto Sánchez, Arani Sinha, Vittorio Turco:
Special Session: Trustworthy Hardware-AI at the Cloud. 1-11 - Dev Mehta, Trey Marcantino, Mohammad Hashemi, Sam Karkache, Dillibabu Shanmugam, Patrick Schaumont, Fatemeh Ganji:
SCAPEgoat: Side-channel Analysis Library. 1-7 - Hasin Ishraq Reefat, Hossein Pourmehrani, Wei Cheng, Claude Carlet, Abderrahman Daif, Cédric Tavernier, Sylvain Guilley, Naghmeh Karimi:
CBM-TI: Code-Based Masking against Glitches by Hybridization with Threshold Implementation. 1-11 - Christopher Bailey:
Reliability Challenges for Advanced Packaging. 1-4 - Kazi Mejbaul Islam, Tambiara Tabassum, Dipal Halder, Sandip Ray:
Special Session: Security Verification of Microelectronic Systems with Integrated AI Accelerators: Scope, Practice, and Challenges. 1-4 - Abhishek Pullela, Ashfakh Huluvallay, Arpan Jain, Zia Abbas, Inhee Lee:
Low-Power Voltage Reference: Review & Progress. 1-5 - Sudipta Paria, Aritra Dasgupta, Swarup Bhunia:
Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages. 1-5 - Yun-Sheng Liu, Min-Hsin Liu, James Chien-Mo Li:
ML-based Adaptive Wafer Sort to Preserve Diagnostic Information. 1-7 - Negar Reiskarimian:
Opportunities for Built-In Self-Test Within Emerging mm-Wave Phased-Array and MIMO Architectures. 1-5 - Arjun Chaudhuri, Bonita Bhaskaran:
Revisiting Microelectronics Resilience and Reliability in the Era of AI. 1 - Kaki Ryan, Cynthia Sturton:
Special Session: Bringing Symbolic Execution to the Security Verification of Hardware Designs. 1-4 - Leonardo Alexandrino De Melo, Rodrigo Possamai Bastos, Alberto Bosio:
MicroFI: TensorFlow Lite based Fault Injection Framework for Microcontrollers. 1-7 - Yuxuan Yin, Rebecca Chen, Varun Thukral, Chen He, Peng Li:
Reliable Board-Level Degradation Prediction with Monotonic Segmented Regression under Noisy Measurement. 1-7 - Cesar A. Sánchez-Martínez, Paulo Lopez-Meyer, Andres Viveros-Wacher:
Artificial Bee Colony Optimization to Accelerate High-Speed Serial I/O Tx Equalization. 1-5 - Anand Menon, Samit Shahnawaz Miftah, Amisha Srivastava, Shamik Kundu, Shovik Kundu, Arnab Raha, Suvadeep Banerjee, Deepak Mathaikutty, Kanad Basu:
OpenAssert: Towards Secure Assertion Generation using Large Language Models. 1-5 - Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Kun-Han Tsai, Janusz Rajski:
Timing-Verification Test Generation Targeting Small Delay Defects. 1-7 - Rui Shi, Seda Ogrenci:
SPRING: Systematic Profiling of Randomly Interconnected Neural Networks Generated by HLS. 1-5 - Mehmet Onder, Lakshmanan Balasubramanian, Rubin A. Parekhji, Suriyaprakash Natarajan, Sule Ozev:
Defect Severity Analysis for Analog Circuits Using Zoom Search and Hierarchical Fault Simulation. 1-7 - Fei Su, Yogesh Varma, John Holm, Drew Walton:
Innovation Practices Track: Industry RAS/SDC Innovative Practices - from Silicon to Mega Fleets. 1 - Katayoon Yahyaei, M. Shafkat M. Khan, Navid Asadizanjani:
From Design to Inspection: Can Inspection-aware Design Enhance Reliability in Advanced Packaging? 1-5 - Kexin Li, Armagan Dascurcu, Hari Vemuri, Harish Krishnaswamy:
Characterization and All-Region Virtual-Source Modeling of 40 nm GaN HEMT Technology for High Frequency IC Design. 1-5 - Akashdeep Saha, Prithwish Basu Roy, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu, Lilas Alrahis:
GLLaMoR: Graph-based Logic Locking by Large Language Models for Enhanced Robustness. 1-5 - Wu-Tung Cheng:
APT: Optimal Tree for Diagnosis Simulation. 1-7 - Nowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar:
LLM-IFT: LLM-Powered Information Flow Tracking for Secure Hardware. 1-5 - Ruben Purdy, Chris Nigh, Wei Li, R. D. Shawn Blanton:
CHEF: CHaracterizing Elusive Logic Circuit Failures. 1-7 - Irith Pomeranz:
Chip Aging and Double Transition Faults. 1-7 - Wei Zou, Artur Pogiel, Albert Au, Martin Keim:
Periodic Non-Destructive Memory BIST for Automotive Applications. 1-7 - Tuan Quang Pham, Sai Sanjeet, Bibhu Datta Sahoo:
Machine Learning Based Calibration Techniques for ADCs: An Overview. 1-5 - Cheng-Hsiang Tsai, Yu-Teng Nien, Guan-You Chen, Mango Chia-Tso Chao:
Test Methodology for Detecting Defect-Based Hold-Time Faults. 1-7 - Amit Ranjan Trivedi, Shamma Nasrin, Priyesh Shukla, Nastaran Darabi, Divake Kumar, Dinithi Jayasuriya, Nethmi Jayasinghe:
MOSAIC: Collaborative Compute-in-Memory µArrays for Flexible and Scalable Deep Learning. 1-4 - Suriyaprakash Natarajan, Saghir A. Shaikh, Wu-Tung Cheng, Sankaran Menon:
Innovation Practices Track: Frontiers in Diagnosis and Debug. 1 - Sohrab Aftabjahani, Wilson Pradeep:
Security Verification and Secure Testing Solutions. 1 - Dipayan Saha, Hasan Al Shaikh, Shams Tarek, Farimah Farahmandi:
Special Session: ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification. 1-5 - Farshad Firouzi, David Z. Pan, Jiaqi Gu, Bahar J. Farahani, Jayeeta Chaudhuri, Ziang Yin, Pingchuan Ma, Peter Domanski, Krishnendu Chakrabarty:
ChipMnd: LLMs for Agile Chip Design. 1-10 - Arjun Chaudhuri:
Hardware Security and Test for AMS Circuits. 1 - Irith Pomeranz:
Fine-Grained Steepening of the Fault Coverage Curve of a Pool of Functional Test Sequences. 1-7 - Omid Halimi Milani, Amanda Nikho, Lauren Mills, Marouane Tliba, Ahmet Enis Çetin, Mohammed H. Elnagar:
Gradient Attention Map Based Verification of Deep Convolutional Neural Networks with Application to X-ray Image Datasets. 1-5 - Shams Tarek, Dipayan Saha, Sujan Kumar Saha, Farimah Farahmandi:
BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection. 1-5 - Ishaan Bassi, Sule Ozev:
DC Stimulus Electrical Calibration of MEMS Accelerometers. 1-7 - Mahta Mayahinia, Mehdi Baradaran Tahoori:
Electromigration Reliability Analysis of SRAM-based Register Files in GPUs and AI Accelerators. 1-4 - Zhiteng Chao, Bin Sun, Hongqin Lyu, Ge Yu, Minjun Wang, Wenxing Li, Zizhen Liu, Jianan Mu, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li:
HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion. 1-7 - Mateo Rendón, Ian Hill, André Ivanov:
Gate Leakage Current Integration-Based Dielectric Breakdown Monitor in a 12nm FinFET Process. 1-7 - Arjun Chaudhuri, Soyed Tuhin Ahmed:
AI for Test : (Innovation Practices Track). 1 - Haneen G. Hezayyin, Mahta Mayahinia, Mehdi Baradaran Tahoori:
Fault Modeling and Testing of ReRAM-based CAM Array. 1-7 - Suma Ayyagari:
Test Complexity in the Semiconductor Landscape. 1-5 - Ching-Yi Chang, Matthew Nigh, John M. Carulli, Yiorgos Makris:
Enhancing Metrology to E-test Correlation Model Accuracy through Process Expertise Integration. 1-7 - Yeqi Wei, Wenjing Rao, Natasha Devroye:
Challenge Selection for Salvaging Faulty APUFs. 1-7 - Partho Bhoumik, Christopher Bailey, Krishnendu Chakrabarty:
Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging*. 1-7 - Emmanuel Nti Darko, Saeid Karimpour, Degang Chen:
High-Accuracy, Cost-Effective Built-In Self-Test Approach for High-Resolution Data Converters. 1-7 - Noah Rajbharti, Esteban Chacon, Muslum Emir Avci, Jennifer Kitchen, Sule Ozev:
A Multi-Step Algorithm to Increase Measurement Accuracy of mm-Wave BIST Using Periodic Structures. 1-5 - Anshuman Chandra, Esteban Garita-Rodríguez, Pradipta Ghosh:
Test, Debug, and Repair for Chiplet-Based Designs. 1
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