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2010 – 2019
- 2017
[c14]Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, Chi-Feng Wu:
Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model. VLSI-DAT 2017: 1-4- 2012
- [c13]Chih-Wea Wang, Chen-Tung Lin, Chun-Chieh Hsu, Ching-Tung Wu, Chi-Feng Wu:
Test for more than pass/fail using on-chip temperature sensor. VLSI-DAT 2012: 1-4
2000 – 2009
- 2007
- [j2]Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
:
STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 541-545 (2007) - 2004
- [c12]Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu:
Failure Factor Based Yield Enhancement for SRAM Designs. DFT 2004: 20-28 - [c11]Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee:
An SOC Test Integration Platform and Its Industrial Realization. ITC 2004: 1213-1222 - 2003
- [c10]Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu:
FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD 2003: 595-598 - [c9]Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories. ITC 2003: 29-38 - [c8]Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
Test and Diagnosis of Word-Oriented Multiport Memories. VTS 2003: 248-253 - 2002
- [j1]Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin:
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. J. Electron. Test. 18(6): 637-647 (2002) - [c7]Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356- - [c6]Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411- - [c5]Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu:
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS 2002: 281-288 - 2001
- [c4]Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang:
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium 2001: 103- - [c3]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC 2001: 301-306 - 2000
- [c2]Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin:
A built-in self-test and self-diagnosis scheme for embedded SRAM. Asian Test Symposium 2000: 45-50 - [c1]Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu:
Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD 2000: 468-471
Coauthor Index
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