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2020 – today
- 2023
[j5]Dimitrios Mangiras
, David G. Chinnery, Giorgos Dimitrakopoulos:
Task-Based Parallel Programming for Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1309-1322 (2023)- [j4]Iris Hui-Ru Jiang, David G. Chinnery, Gracieli Posser, Jens Lienig:
Introduction to the Special Section on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. 28(5): 68:1-68:3 (2023) - [c18]Iris Hui-Ru Jiang, David G. Chinnery:
EDA for Domain Specific Computing: An Introduction for the Panel. ISPD 2023: 205 - [e1]David G. Chinnery, Iris Hui-Ru Jiang:
Proceedings of the 2023 International Symposium on Physical Design, ISPD 2023, Virtual Event, USA, March 26-29, 2023. ACM 2023, ISBN 978-1-4503-9978-4 [contents] - 2022
- [c17]David G. Chinnery, Ankur Sharma:
Integrating LR Gate Sizing in an Industrial Place-and-Route Flow. ISPD 2022: 39-48 - 2021
- [j3]Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos:
Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1672-1686 (2021) - 2020
- [j2]Ankur Sharma, David G. Chinnery, Tiago Reimann, Sarvesh Bhardwaj, Chris Chu:
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1456-1469 (2020) - [c16]Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos:
Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation. ISPD 2020: 87-94
2010 – 2019
- 2019
- [j1]Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery:
Timing-Driven and Placement-Aware Multibit Register Composition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1501-1514 (2019) - [c15]David G. Chinnery:
Session details: Detailed Routing Contest Results. ISPD 2019 - [c14]Ankur Sharma, David G. Chinnery, Chris Chu:
Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach. ISPD 2019: 129-137 - 2017
- [c13]Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery:
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. DAC 2017: 56:1-56:6 - [c12]Ankur Sharma, David G. Chinnery, Shrirang Dhamdhere, Chris Chu:
Rapid gate sizing with fewer iterations of Lagrangian Relaxation. ICCAD 2017: 337-343 - 2015
- [c11]Ankur Sharma, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu:
Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. ICCAD 2015: 426-433 - [c10]Ismail S. Bustany, David G. Chinnery, Joseph R. Shinnerl, Vladimir Yutsis:
ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement. ISPD 2015: 157-164 - 2014
- [c9]Vladimir Yutsis, Ismail Bustany, David G. Chinnery, Joseph R. Shinnerl, Wen-Hao Liu:
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement. ISPD 2014: 161-168 - 2013
- [c8]David G. Chinnery:
High performance and low power design techniques for ASIC and custom in nanometer technologies. ISPD 2013: 25-32
2000 – 2009
- 2007
- [b2]David G. Chinnery, Kurt Keutzer:
Closing the Power Gap between ASIC and Custom - Tools and Techniques for Low Power Design. Springer 2007, ISBN 978-0-387-25763-1, pp. I-XII, 1-384 - 2005
- [c7]David G. Chinnery, Kurt Keutzer:
Closing the power gap between ASIC and custom: an ASIC perspective. DAC 2005: 275-280 - [c6]David G. Chinnery, Kurt Keutzer:
Linear programming for sizing, Vth and Vdd assignment. ISLPED 2005: 149-154 - 2004
- [b1]David G. Chinnery, Kurt Keutzer:
Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design. Springer 2004, ISBN 978-1-4020-7113-3, pp. I-XIV, 1-414 - 2003
- [c5]Masayuki Ito, David G. Chinnery, Kurt Keutzer:
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. ICCD 2003: 21- - [c4]David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer:
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ISLPED 2003: 158-163 - 2001
- [c3]David G. Chinnery, Borivoje Nikolic, Kurt Keutzer:
Achieving 550Mhz in an ASIC Methodology. DAC 2001: 420-425 - [c2]Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer:
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. ICCD 2001: 82-88 - 2000
- [c1]David G. Chinnery, Kurt Keutzer:
Closing the gap between ASIC and custom: an ASIC perspective. DAC 2000: 637-642
Coauthor Index
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