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ORCIDNicholas P. Carter
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2010 – 2019
- 2013
[c20]Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase
, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu:
Runnemede: An architecture for Ubiquitous High-Performance Computing. HPCA 2013: 198-209- 2011
- [c19]Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V. Adve, Vikram S. Adve, Nicholas P. Carter, Ching-Tsun Chou:
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism. PACT 2011: 155-166 - 2010
- [c18]André DeHon, Heather M. Quinn, Nicholas P. Carter:
Vision for cross-layer optimization to address the dual challenges of energy and reliability. DATE 2010: 1017-1022 - [c17]Nicholas P. Carter, Helia Naeimi, Donald S. Gardner:
Design techniques for cross-layer resilience. DATE 2010: 1023-1028
2000 – 2009
- 2007
- [j10]Nitin Navale, Erica Lundgren, Nicholas P. Carter:
A magnetoelectronic register file cell for a self-checkpointing microprocessor. Int. J. Circuit Theory Appl. 35(3): 371-390 (2007) - [j9]Richard B. Kujoth, Chi-Wei Wang, Jeffrey J. Cook, Derek B. Gottlieb, Nicholas P. Carter:
A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor. Microprocess. Microsystems 31(2): 146-159 (2007) - [j8]Love Kothari, Nicholas P. Carter:
Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices. IEEE Trans. Computers 56(2): 161-173 (2007) - 2006
- [j7]Nicholas P. Carter, Azmat Hussain:
Modeling wire delay, area, power, and performance in a simulation infrastructure. IBM J. Res. Dev. 50(2-3): 311-320 (2006) - 2005
- [j6]Pratyush Das Kanungo, Alexandra Imre, Bin Wu, Alexei O. Orlov, Gregory L. Snider, Wolfgang Porod, Nicholas P. Carter:
Gated hybrid Hall effect device on silicon. Microelectron. J. 36(3-6): 294-297 (2005) - [c16]Nicholas P. Carter, Steve Ferrera, Love Kothari, Stanley Ye:
Hall-effect circuits and architectures for non-volatile system design. ECCTD 2005: 131-134 - [c15]Chi-Wei Wang, Nicholas P. Carter, Richard B. Kujoth, Jeffrey J. Cook, Derek B. Gottlieb:
Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor. FPL 2005: 57-64 - 2004
- [j5]Jeffrey M. Stine, Nicholas P. Carter, José Flich:
Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction. IEEE Comput. Archit. Lett. 3 (2004) - [j4]Nicholas P. Carter, Steve Ferrera:
Reconfigurable magnetoelectronic circuits for threshold logic. Int. J. Circuit Theory Appl. 32(5): 363-382 (2004) - [c14]Steve Ferrera, Nicholas P. Carter:
A magnetoelectronic macrocell employing reconfigurable threshold logic. FPGA 2004: 143-151 - [c13]Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter:
A reconfigurable unit for a clustered programmable-reconfigurable processor. FPGA 2004: 200-209 - 2003
- [c12]Steve Ferrera, Nicholas P. Carter:
Reconfigurable Circuits Using Hybrid Hall Effect Devices. FPL 2003: 1-10 - [c11]Jeffrey J. Cook, Lee Baugh, Derek B. Gottlieb, Nicholas P. Carter:
Mapping computation kernels to clustered programmable-reconfigurable processors. FPT 2003: 435-438 - [c10]Derek B. Gottlieb, Nicholas P. Carter:
Microprocessor Interfacing Laboratory. MSE 2003: 106-107 - 2002
- [c9]Joshua D. Walstrom, Jeffrey J. Cook, Derek B. Gottlieb, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter:
The Design of the Amalgam Reconfigurable Cluster. FCCM 2002: 309-310 - [c8]Jeffrey J. Cook, Derek B. Gottlieb, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter:
Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor. FCCM 2002: 311- - [c7]Derek B. Gottlieb, Jeffrey J. Cook, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter:
Clustered programmable-reconfigurable processors. FPT 2002: 134-141 - 2000
- [c6]Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang:
Processor Mechanisms for Software Shared Memory. ISHPC 2000: 120-133
1990 – 1999
- 1999
- [b1]Nicholas P. Carter:
Processor mechanisms for software shared memory. Massachusetts Institute of Technology, Cambridge, MA, USA, 1999 - 1998
- [j3]Whay Sing Lee, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Andrew Chang:
An Efficient, Protected Message Interface. Computer 31(11): 69-75 (1998) - [c5]Andrew Chang, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Whay Sing Lee:
The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline. ICCD 1998: 474-481 - [c4]Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee:
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. ISCA 1998: 306-317 - 1997
- [j2]Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee:
The M-machine multicomputer. Int. J. Parallel Program. 25(3): 183-212 (1997) - 1995
- [c3]Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee:
The M-Machine multicomputer. MICRO 1995: 146-156 - 1994
- [c2]Nicholas P. Carter, Stephen W. Keckler, William J. Dally:
Hardware Support for Fast Capability-based Addressing. ASPLOS 1994: 319-327 - [c1]Nicholas P. Carter:
Conversion of the Haydn symphonies into electronic form using automatic score recognition: a pilot study. Document Recognition 1994: 279-290 - 1992
- [j1]Nicholas P. Carter:
Segmentation and preliminary recognition of madrigals notated in white mensural notation. Mach. Vis. Appl. 5(3): 223-229 (1992)
Coauthor Index
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