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ORCIDAtin Mukherjee 0001
Person information
- affiliation: National Institute of Technology Rourkela, India
- affiliation (PhD 2017): Indian Institute of Technology, Kharagpur, Department of Electronics & Electrical Communication Engineering, India
Other persons with the same name
- Atin Mukherjee 0002 — Neotia Institute of Technology, Management and Science
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2020 – today
- 2024
[j10]Sandeep Kumar
, Atin Mukherjee:
Low cost and high performance double-node upset resilient latch for low orbit space applications. Int. J. Circuit Theory Appl. 52(5): 2534-2549 (2024)- [j9]Anusaka Gon, Atin Mukherjee:
Design of a low-area hardware architecture to predict early signs of sudden cardiac arrests. Microprocess. Microsystems 109: 105082 (2024) - 2023
- [j8]Anusaka Gon, Atin Mukherjee:
FPGA-Based Low-Cost Architecture for R-Peak Detection and Heart-Rate Calculation Using Lifting-Based Discrete Wavelet Transform. Circuits Syst. Signal Process. 42(1): 580-600 (2023) - [j7]Sandeep Kumar, Atin Mukherjee:
High performance radiation-hardened SRAM cell design for robust applications. Microelectron. J. 140: 105934 (2023) - [c7]Anwesh Kumar Samal, Sandeep Kumar, Atin Mukherjee:
Design of Single Node Upset Resilient Latch for Low Power, Low Cost and Highly Robust Applications. ITC-Asia 2023: 1-5 - 2021
- [j6]Sandeep Kumar, Atin Mukherjee:
A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2076-2085 (2021) - [c6]Sandeep Kumar, Atin Mukherjee:
A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch Design. DFT 2021: 1-6 - 2020
- [c5]Atin Mukherjee:
Defect Tolerant Approach for Reliable Majority Voter Design Using Quadded Transistor Logic. TENCON 2020: 165-169
2010 – 2019
- 2019
- [j5]Atin Mukherjee, Anindya Sundar Dhar:
Triple transistor based triple modular redundancy with embedded voter circuit. Microelectron. J. 87: 101-109 (2019) - [c4]Atin Mukherjee, Anindya Sundar Dhar:
Defect Tolerant Majority Voter Design Using Triple Transistor Redundancy. iSES 2019: 63-68 - 2018
- [j4]Atin Mukherjee, Anindya Sundar Dhar:
Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method. Circuits Syst. Signal Process. 37(12): 5595-5615 (2018) - 2017
- [j3]Atin Mukherjee, Anindya Sundar Dhar:
Triple transistor based fault tolerance for resource constrained applications. Microelectron. J. 68: 1-6 (2017) - 2016
- [j2]Atin Mukherjee, Anindya Sundar Dhar:
Choice of granularity for reliable circuit design using dynamic reconfiguration. Microelectron. Reliab. 63: 291-303 (2016) - 2015
- [j1]Atin Mukherjee, Anindya Sundar Dhar:
Real-time fault-tolerance with hot-standby topology for conditional sum adder. Microelectron. Reliab. 55(3-4): 704-712 (2015) - [c3]Atin Mukherjee, Anindya Sundar Dhar:
New triple-transistor based defect-tolerant systems for reliable digital architectures. ISCAS 2015: 1917-1920 - 2012
- [c2]Atin Mukherjee, Anindya Sundar Dhar:
Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture. ISED 2012: 92-96 - [c1]Atin Mukherjee, Anindya Sundar Dhar:
Design of a Fault-Tolerant Conditional Sum Adder. VDAT 2012: 217-222
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