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2020 – today
- 2020
[c9]Yi-Shyuan Chiang
, Ruei-Che Chang, Yi-Lin Chuang, Shih-Ya Chou, Hao-Ping Lee, I-Ju Lin, Jian-Hua Jiang Chen, Yung-Ju Chang:
Exploring the Design Space of User-System Communication for Smart-home Routine Assistants. CHI 2020: 1-14
2010 – 2019
- 2014
- [j4]Hong-Ting Lin, Yi-Lin Chuang, Zong-Han Yang, Tsung-Yi Ho:
Pulsed-Latch Utilization for Clock-Tree Power Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 721-733 (2014) - 2012
- [c8]Da-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang:
Statistical thermal modeling and optimization considering leakage power variations. DATE 2012: 605-610 - 2011
- [j3]Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang:
Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1649-1662 (2011) - [j2]Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang:
Pulsed-Latch Aware Placement for Timing-Integrity Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1856-1869 (2011) - [c7]Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu:
PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. ICCAD 2011: 85-90 - [c6]Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho:
Pulsed-latch-based clock tree migration for dynamic power reduction. ISLPED 2011: 39-44 - 2010
- [c5]Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang:
Pulsed-latch aware placement for timing-integrity optimization. DAC 2010: 280-285 - [c4]Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan:
Design-hierarchy aware mixed-size placement for routability optimization. ICCAD 2010: 663-668
2000 – 2009
- 2009
- [c3]Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang:
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. ICCAD 2009: 666-673 - 2008
- [j1]Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
Effective Wire Models for X-Architecture Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 654-658 (2008) - [c2]Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang:
Constraint graph-based macro placement for modern mixed-size circuit designs. ICCAD 2008: 218-223 - 2007
- [c1]Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
X-architecture placement based on effective wire models. ISPD 2007: 87-94
Coauthor Index
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