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ORCIDThomas C. P. Chau
Person information
- unicode name: 周俊邦
- affiliation: Google, USA
- affiliation: Neubla, UK
- affiliation (former): Samsung AI Center, Cambridge, UK
- affiliation (former): Intel Corporation, High Wycombe, UK
- affiliation (former): Altera, High Wycombe, UK
- affiliation (former, PhD 2014): Imperial College London, Department of Computing, UK
- affiliation (former): Chinese University of Hong Kong, Department of Computer Science and Engineering, Hong Kong
Other persons with the same name
- Thomas Chau 0002 — University of Calgary, Department of Computer Science, Calgary, AB, Canada
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2020 – today
- 2023
[c26]Lichuan Xiang, Lukasz Dudziak, Mohamed S. Abdelfattah, Thomas C. P. Chau, Nicholas D. Lane, Hongkai Wen:
Zero-Cost Operation Scoring in Differentiable Architecture Search. AAAI 2023: 10453-10463- 2022
- [c25]Hongxiang Fan, Thomas Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah:
Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. MICRO 2022: 599-615 - [c24]Thomas Chau, Lukasz Dudziak, Hongkai Wen, Nicholas D. Lane, Mohamed S. Abdelfattah:
BLOX: Macro Neural Architecture Search Benchmark and Algorithms. NeurIPS 2022 - [e1]Lin Gan, Yu Wang, Wei Xue, Thomas Chau:
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 18th International Symposium, ARC 2022, Virtual Event, September 19-20, 2022, Proceedings. Lecture Notes in Computer Science 13569, Springer 2022, ISBN 978-3-031-19982-0 [contents] - [i5]Hongxiang Fan, Thomas Chun-Pong Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah:
Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. CoRR abs/2209.09570 (2022) - [i4]Thomas Chun-Pong Chau, Lukasz Dudziak, Hongkai Wen, Nicholas Donald Lane, Mohamed S. Abdelfattah:
BLOX: Macro Neural Architecture Search Benchmark and Algorithms. CoRR abs/2210.07271 (2022) - 2021
- [c23]Abhinav Mehrotra, Alberto Gil C. P. Ramos, Sourav Bhattacharya, Lukasz Dudziak, Ravichander Vipperla, Thomas Chau, Mohamed S. Abdelfattah, Samin Ishtiaq, Nicholas Donald Lane:
NAS-Bench-ASR: Reproducible Neural Architecture Search for Speech Recognition. ICLR 2021 - [i3]Lichuan Xiang, Lukasz Dudziak, Mohamed S. Abdelfattah, Thomas Chau, Nicholas D. Lane, Hongkai Wen:
Zero-Cost Proxies Meet Differentiable Architecture Search. CoRR abs/2106.06799 (2021) - 2020
- [c22]Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane:
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator. DAC 2020: 1-6 - [c21]Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane:
Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture Search. FPGA 2020: 315 - [c20]Lukasz Dudziak, Thomas Chau, Mohamed S. Abdelfattah, Royson Lee, Hyeji Kim, Nicholas D. Lane:
BRP-NAS: Prediction-based NAS using GCNs. NeurIPS 2020 - [i2]Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane:
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator. CoRR abs/2002.05022 (2020) - [i1]Thomas Chau, Lukasz Dudziak, Mohamed S. Abdelfattah, Royson Lee, Hyeji Kim, Nicholas D. Lane:
BRP-NAS: Prediction-based NAS using GCNs. CoRR abs/2007.08668 (2020)
2010 – 2019
- 2019
- [c19]Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Thomas Chau:
Transparent Heterogeneous Cloud Acceleration. ASAP 2019: 33 - 2018
- [c18]Shengjia Shao, Jason Tsai, Michal Mysior, Wayne Luk, Thomas Chau, Alexander Warren, Ben Jeppesen:
Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control. ASAP 2018: 1-8 - 2017
- [j6]Thomas Chau, Pavel Burovskiy, Michael J. Flynn, Wayne Luk:
Chapter Two - Advances in Dataflow Systems. Adv. Comput. 106: 21-62 (2017) - 2016
- [c17]Ben P. Jeppesen, Andrew Crosland, Thomas Chau:
An FPGA-based platform for integrated power and motion control. IECON 2016: 2684-2689 - [c16]Rocco Morello, Federico Baronti, X. Tian, Thomas Chau, Roberto Di Rienzo
, Roberto Roncella, B. P. Jeppesen, W. H. Lin, T. Ikushima, Roberto Saletti:
Hardware-in-the-loop simulation of FPGA-based state estimators for electric vehicle batteries. ISIE 2016: 280-285 - 2015
- [j5]Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan M. Maciejowski, Peter Y. K. Cheung, Wayne Luk:
Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 7(4): 36:1-36:17 (2015) - [j4]Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell:
Automating Elimination of Idle Functions by Runtime Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 8(3): 15:1-15:28 (2015) - [c15]Shengjia Shao, Liucheng Guo, Ce Guo, Thomas C. P. Chau, David B. Thomas, Wayne Luk, Stephen Weston:
Recursive pipelined genetic propagation for bilevel optimisation. FPL 2015: 1-6 - 2014
- [b1]Thomas Chun-Pong Chau:
Optimising reconfigurable systems for real-time applications. Imperial College London, UK, 2014 - [c14]Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk:
SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. FCCM 2014: 141-148 - [c13]Maciej Kurek, Tobias Becker, Thomas C. P. Chau, Wayne Luk:
Automating Optimization of Reconfigurable Designs. FCCM 2014: 210-213 - 2013
- [j3]Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski:
Accelerating sequential Monte Carlo method for real-time air traffic management. SIGARCH Comput. Archit. News 41(5): 35-40 (2013) - [j2]S. Man Ho Ho, Yanqing Ai, Thomas Chun-Pong Chau, Steve C. L. Yuen, Oliver Chiu-sing Choy, Philip Heng Wai Leong, Kong-Pang Pun:
Architecture and Design Flow for a Highly Efficient Structured ASIC. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 424-433 (2013) - [c12]Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski:
Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. ARC 2013: 1-12 - [c11]Alison Eele, Jan M. Maciejowski, Thomas Chau, Wayne Luk:
Parallelisation of Sequential Monte Carlo for real-time control in air traffic management. CDC 2013: 4859-4864 - [c10]Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu:
Automating Elimination of Idle Functions by Run-Time Reconfiguration. FCCM 2013: 97-104 - [c9]Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu:
Automating resource optimisation in reconfigurable design (abstract only). FPGA 2013: 275 - [c8]Thomas C. P. Chau, Ka-Wai Kwok, Gary C. T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse, Peter Y. K. Cheung, Wayne Luk:
Acceleration of real-time Proximity Query for dynamic active constraints. FPT 2013: 206-213 - 2012
- [j1]Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung:
Roberts: reconfigurable platform for benchmarking real-time systems. SIGARCH Comput. Archit. News 40(5): 10-15 (2012) - [c7]Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski:
Adaptive Sequential Monte Carlo approach for real-time applications. FPL 2012: 527-530 - 2010
- [c6]Steve C. L. Yuen, Yanqing Ai, Brian P. W. Chan, Thomas C. P. Chau, Sam M. H. Ho, Oscar K. L. Lau, Kong-Pang Pun, Philip Heng Wai Leong, Oliver C. S. Choy:
Rapid prototyping on a structured ASIC fabric. ASP-DAC 2010: 379-380 - [c5]Thomas C. P. Chau, David W. L. Wu, Yanqing Ai, Brian P. W. Chan, Sam M. H. Ho, Oscar K. L. Lau, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Philip Heng Wai Leong:
Design of a single layer programmable Structured ASIC library. DDECS 2010: 32-35 - [c4]Sam M. H. Ho, Steve C. L. Yuen, Hiu Ching Poon, Thomas C. P. Chau, Yanqing Ai, Philip Heng Wai Leong, Oliver C. S. Choy, Kong-Pang Pun:
Structured ASIC: Methodology and comparison. FPT 2010: 377-380
2000 – 2009
- 2009
- [c3]Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang:
A comparison of via-programmable gate array logic cell circuits. FPGA 2009: 53-62 - [c2]Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong:
A detailed delay path model for FPGAs. FPT 2009: 96-103 - [c1]Thomas C. P. Chau, S. Man Ho Ho, Philip Heng Wai Leong, Peter Zipf, Manfred Glesner:
Generation of Synthetic Floating-Point benchmark circuits. IPDPS 2009: 1-9
Coauthor Index
aka: Nicholas Donald Lane
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