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Dilip P. Vasudevan
Person information
- affiliation: Lawrence Berkeley National Labs, Berkeley, CA, USA
- affiliation (former): University College Cork, Ireland
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2020 – today
- 2024
- [c25]Hasita Veluri, Dilip Vasudevan:
BMX-FPCA: 3D Beyond-Moore Flexible Field Programmable Crossbar Array Architecture. ISQED 2024: 1-9 - 2023
- [c24]Maximilian H. Bremer, Nirmalendu Patra, Tan Nguyen, Dilip Vasudevan, Cy P. Chan:
Benefits of Optimistic Parallel Discrete Event Simulation for Network-on-Chip Simulation. DS-RT 2023: 30-39 - 2021
- [j8]Georgios Tzimpragos
, Advait Madhavan, Dilip Vasudevan, Dmitri B. Strukov, Timothy Sherwood
:
In-sensor classification with boosted race trees. Commun. ACM 64(6): 99-105 (2021) - [j7]Georgios Tzimpragos
, Jennifer Volk, Dilip Vasudevan
, Nestan Tsiskaridze, George Michelogiannakis
, Advait Madhavan, John Shalf
, Timothy Sherwood
:
Temporal Computing With Superconductors. IEEE Micro 41(3): 71-79 (2021) - [c23]George Michelogiannakis
, Darren Lyles
, Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Dilip Vasudevan
, Anastasiia Butko:
SRNoC: A Statically-Scheduled Circuit-Switched Superconducting Race Logic NoC. IPDPS 2021: 1046-1055 - 2020
- [j6]Weilong Cui
, Georgios Tzimpragos
, Yu Tao
, Joseph McMahan, Deeksha Dangwal, Nestan Tsiskaridze, George Michelogiannakis, Dilip P. Vasudevan
, Timothy Sherwood
:
Language Support for Navigating Architecture Design in Closed Form. ACM J. Emerg. Technol. Comput. Syst. 16(1): 9:1-9:28 (2020) - [c22]Georgios Tzimpragos
, Dilip Vasudevan
, Nestan Tsiskaridze, George Michelogiannakis
, Advait Madhavan, Jennifer Volk, John Shalf
, Timothy Sherwood
:
A Computational Temporal Logic for Superconducting Accelerators. ASPLOS 2020: 435-448
2010 – 2019
- 2019
- [c21]Georgios Tzimpragos
, Advait Madhavan, Dilip Vasudevan
, Dmitri B. Strukov
, Timothy Sherwood
:
Boosted Race Trees for Low Energy Classification. ASPLOS 2019: 215-228 - [c20]Dilip P. Vasudevan
, George Michelogiannakis
, David Donofrio, John Shalf
:
PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments. ISPASS 2019: 139-140 - [c19]Sebastian Werner, Pouya Fotouhi
, Xian Xiao, Marjan Fariborz, S. J. Ben Yoo, George Michelogiannakis
, Dilip P. Vasudevan
:
3D photonics as enabling technology for deep 3D DRAM stacking. MEMSYS 2019: 206-221 - 2017
- [c18]Dilip P. Vasudevan, George Michelogiannakis
, David Donofrio, John Shalf
:
CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices. NANOARCH 2017: 117-118 - [c17]Dilip P. Vasudevan, Anastasiia Butko, George Michelogiannakis
, David Donofrio, John Shalf
:
Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies. ISC Workshops 2017: 115-123 - 2015
- [j5]Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati:
10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture. SIGARCH Comput. Archit. News 43(2): 2-9 (2015) - [j4]Abhishek Roy, Alicia Klinefelter, Farah B. Yahya, Xing Chen, Luisa Patricia Gonzalez-Guerrero, Christopher J. Lukas
, Divya Akella Kamakshi, James Boley, Kyle Craig, Muhammad Faisal, Seunghyun Oh, Nathan E. Roberts, Yousef Shakhsheer, Aatmesh Shrivastava, Dilip P. Vasudevan, David D. Wentzloff, Benton H. Calhoun:
A 6.45 μW Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems. IEEE Trans. Biomed. Circuits Syst. 9(6): 862-874 (2015) - [c16]Dilip P. Vasudevan, Andrew A. Chien:
The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data. ACM Great Lakes Symposium on VLSI 2015: 103-106 - 2012
- [j3]Jiaoyan Chen, Dilip P. Vasudevan, Michel P. Schellekens, Emanuel M. Popovici:
Ultra Low Power Asynchronous Charge Sharing Logic. J. Low Power Electron. 8(4): 526-534 (2012) - [c15]Jiaoyan Chen, Emanuel M. Popovici, Dilip P. Vasudevan, Michel P. Schellekens:
Ultra Low Power Booth Multiplier Using Asynchronous Logic. ASYNC 2012: 81-88 - 2011
- [c14]Xiaodong Wang, Dilip P. Vasudevan, Hsien-Hsin S. Lee:
Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing. 3DIC 2011: 1-8 - [c13]Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens:
Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder. DSD 2011: 301-308 - 2010
- [c12]Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens:
Reversible online BIST using bidirectional BILBO. Conf. Computing Frontiers 2010: 257-266 - [c11]Tingcong Ye, Dilip P. Vasudevan, Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens:
Static Average Case Power Estimation Technique for Block Ciphers. DSD 2010: 689-696 - [c10]Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens, Peter Gillen:
Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations. ICECS 2010: 434-437
2000 – 2009
- 2008
- [c9]Dilip P. Vasudevan, Aristides Efthymiou
:
A Partial Scan Based Test Generation for Asynchronous Circuits. DDECS 2008: 186-189 - 2007
- [j2]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(12): 2696-2705 (2007) - 2006
- [j1]Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson:
Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. 55(2): 406-414 (2006) - [c8]Jia Di, Dilip P. Vasudevan:
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. DELTA 2006: 149-156 - 2005
- [c7]Dilip P. Vasudevan, Parag K. Lala:
A Technique for Modular Design of Self-Checking Carry-Select Adder. DFT 2005: 325-333 - [c6]Jia Di, Parag K. Lala, Dilip P. Vasudevan:
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. DFT 2005: 371-379 - [c5]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
CMOS Realization of Online Testable Reversible Logic Gates. ISVLSI 2005: 309-310 - 2004
- [c4]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
A Novel Approach for On-line Testable Reversible Logic Circuit Desig. Asian Test Symposium 2004: 325-330 - [c3]Dilip P. Vasudevan, Parag K. Lala:
A New Reversible Logic Gate and its Applications. ESA/VLSI 2004: 480-484 - [c2]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
Online Testable Reversible Logic Circuit Design using NAND Blocks. DFT 2004: 324-331 - [c1]Dilip P. Vasudevan, James Patrick Parkerson, Parag K. Lala:
Logic implementation using a reversible gate. Circuits, Signals, and Systems 2004: 452-456
Coauthor Index
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last updated on 2024-08-08 19:16 CEST by the dblp team
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