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Rajeev Balasubramonian
Person information
- affiliation: University of Utah, Salt Lake City, Utah, USA
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2020 – today
- 2024
- [c69]Lin Jia
, James Patrick Mcmahon
, Sumanth Gudaparthi
, Shreyas Singh
, Rajeev Balasubramonian
:
PATHFINDER: Practical Real-Time Learning for Data Prefetching. ASPLOS (3) 2024: 785-800 - 2023
- [j17]Sarabjeet Singh
, Xiong Fan
, Ananth Krishna Prasad
, Lin Jia, Anirban Nag, Rajeev Balasubramonian
, Mahdi Nazm Bojnordi
, Elaine Shi:
XCRYPT: Accelerating Lattice-Based Cryptography With Memristor Crossbar Arrays. IEEE Micro 43(5): 45-54 (2023) - [i2]Sarabjeet Singh, Xiong Fan, Ananth Krishna Prasad, Lin Jia, Anirban Nag, Rajeev Balasubramonian, Mahdi Nazm Bojnordi, Elaine Shi:
XCRYPT: Accelerating Lattice Based Cryptography with Memristor Crossbar Arrays. CoRR abs/2302.00095 (2023) - 2022
- [j16]Amlan Ganguly
, Sergi Abadal
, Ishan G. Thakkar
, Natalie Enright Jerger
, Marc D. Riedel
, Masoud Babaie
, Rajeev Balasubramonian, Abu Sebastian
, Sudeep Pasricha
, Baris Taskin
:
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion. IEEE Micro 42(3): 40-49 (2022) - [j15]Zhao Chang
, Dong Xie
, Feifei Li, Jeff M. Phillips, Rajeev Balasubramonian:
Efficient Oblivious Query Processing for Range and kNN Queries. IEEE Trans. Knowl. Data Eng. 34(12): 5741-5754 (2022) - [c68]Sumanth Gudaparthi, Sarabjeet Singh, Surya Narayanan, Rajeev Balasubramonian, Visvesh Sathe:
CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration. HPCA 2022: 876-891 - [c67]Zhao Chang
, Dong Xie
, Feifei Li, Jeff M. Phillips, Rajeev Balasubramonian:
Efficient and Oblivious Query Processing for Range and kNN Queries (Extended Abstract). ICDE 2022: 1487-1488 - 2021
- [c66]C. N. Ramachandra, Anirban Nag, Rajeev Balasubramonian, Gurpreet S. Kalsi, Kamlesh R. Pillai, Sreenivas Subramoney:
ONT-X: An FPGA Approach to Real-time Portable Genomic Analysis. FCCM 2021: 268-269 - [c65]Adarsh Patil
, Vijay Nagarajan
, Rajeev Balasubramonian, Nicolai Oswald:
Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication. ISCA 2021: 526-539 - [c64]Anirban Nag, Rajeev Balasubramonian:
OrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations. MICRO 2021: 298-310 - 2020
- [c63]Surya Narayanan, Karl Taht, Rajeev Balasubramonian, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks. ISCA 2020: 349-362 - [c62]Meysam Taassori, Rajeev Balasubramonian, Siddhartha Chhabra, Alaa R. Alameldeen, Manjula Peddireddy, Rajat Agarwal, Ryan Stutsman:
Compact Leakage-Free Support for Integrity and Reliability. ISCA 2020: 735-748
2010 – 2019
- 2019
- [b2]Rajeev Balasubramonian:
Innovations in the Memory System. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2019, ISBN 978-3-031-00635-7 - [c61]Chandrasekhar Nagarajan, Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari
:
ρ: Relaxed Hierarchical ORAM. ASPLOS 2019: 659-671 - [c60]Karl Taht, James Greensky, Rajeev Balasubramonian:
The POP Detector: A Lightweight Online Program Phase Detection Framework. ISPASS 2019: 48-57 - [c59]Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin
, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon:
Wire-Aware Architecture and Dataflow for CNN Accelerators. MICRO 2019: 1-13 - [c58]Anirban Nag, C. N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin
, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon:
GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment. MICRO 2019: 334-346 - 2018
- [j14]Anirban Nag, Rajeev Balasubramonian, Vivek Srikumar, Ross Walker, Ali Shafiee, John Paul Strachan, Naveen Muralimanohar:
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. IEEE Micro 38(5): 41-49 (2018) - [c57]Meysam Taassori, Ali Shafiee, Rajeev Balasubramonian:
VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures. ASPLOS 2018: 665-678 - [c56]Karl Taht, Surya Narayanan, Rajeev Balasubramonian:
A Case for Dynamic Activation Quantization in CNNs. EMC2@ASPLOS 2018: 4-8 - [c55]Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian:
Moving CNN Accelerator Computations Closer to Data. EMC2@ASPLOS 2018: 34-38 - [c54]Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari
, Feifei Li:
Secure DIMM: Moving ORAM Primitives Closer to Memory. HPCA 2018: 428-440 - [c53]Andrew Vuong, Ali Shafiee, Meysam Taassori, Rajeev Balasubramonian:
An MLP-aware leakage-free memory controller. HASP@ISCA 2018: 4:1-4:7 - [i1]Anirban Nag, Ali Shafiee, Rajeev Balasubramonian, Vivek Srikumar, Naveen Muralimanohar:
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. CoRR abs/1803.06913 (2018) - 2017
- [j13]Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, Vaishnav Srinivas
:
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories. ACM Trans. Archit. Code Optim. 14(2): 14:1-14:25 (2017) - [c52]Karl Taht, Rajeev Balasubramonian:
Introspective Computing. PACT 2017: 371 - [c51]Surya Narayanan, Ali Shafiee, Rajeev Balasubramonian:
INXS: Bridging the throughput and energy gap for spiking neural networks. IJCNN 2017: 2451-2459 - 2016
- [j12]Rajeev Balasubramonian, Boris Grot
:
Near-Data Processing [Guest editors' introduction]. IEEE Micro 36(1): 4-5 (2016) - [c50]Arjun Deb, Paolo Faraboschi
, Ali Shafiee, Naveen Muralimanohar, Rajeev Balasubramonian, Robert Schreiber:
Enabling technologies for memory compression: Metadata, mapping, and prediction. ICCD 2016: 17-24 - [c49]Meysam Taassori, Ali Shafiee, Rajeev Balasubramonian:
Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system. ICCD 2016: 217-224 - [c48]Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams
, Vivek Srikumar:
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. ISCA 2016: 14-26 - [c47]Manjunath Shevgoor, Rajeev Balasubramonian, Niladrish Chatterjee, Jung-Sik Kim:
Addressing service interruptions in memory with thread-to-rank assignment. ISPASS 2016: 24-35 - 2015
- [c46]Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu
, Yuan Xie:
Overcoming the challenges of crossbar resistive memory architectures. HPCA 2015: 476-488 - [c45]Seth H. Pugsley, Arjun Deb, Rajeev Balasubramonian, Feifei Li:
Fixed-function hardware sorting accelerators for near data MapReduce execution. ICCD 2015: 439-442 - [c44]Manjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian, Yoocharn Jeon:
Improving memristor memory with sneak current sharing. ICCD 2015: 549-556 - [c43]Ali Shafiee, Akhila Gundu, Manjunath Shevgoor, Rajeev Balasubramonian, Mohit Tiwari
:
Avoiding information leakage in the memory controller with fixed service policies. MICRO 2015: 89-101 - [c42]Manjunath Shevgoor, Sahil Koladiya, Rajeev Balasubramonian, Chris Wilkerson, Seth H. Pugsley, Zeshan Chishti:
Efficiently prefetching complex address patterns. MICRO 2015: 141-152 - 2014
- [j11]Rajeev Balasubramonian, Jichuan Chang, Troy Manning, Jaime H. Moreno, Richard Murphy, Ravi Nair, Steven Swanson
:
Near-Data Processing: Insights from a MICRO-46 Workshop. IEEE Micro 34(4): 36-42 (2014) - [j10]Seth H. Pugsley, Jeffrey Jestes, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, Alper Buyuktosunoglu, Al Davis, Feifei Li:
Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads. IEEE Micro 34(4): 44-52 (2014) - [c41]Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian:
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers. HPCA 2014: 626-637 - [c40]Ali Shafiee, Meysam Taassori, Rajeev Balasubramonian, Al Davis:
MemZip: Exploring unconventional benefits from memory compression. HPCA 2014: 638-649 - [c39]Akhila Gundu, Gita Sreekumar, Ali Shafiee, Seth H. Pugsley, Hardik B. Jain, Rajeev Balasubramonian, Mohit Tiwari
:
Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller. HASP@ISCA 2014: 11:1-11:5 - [c38]Seth H. Pugsley, Jeffrey Jestes, Huihui Zhang, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, Alper Buyuktosunoglu, Al Davis, Feifei Li:
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads. ISPASS 2014: 190-200 - [c37]Niladrish Chatterjee, Mike O'Connor
, Gabriel H. Loh, Nuwan Jayasena, Rajeev Balasubramonian:
Managing DRAM Latency Divergence in Irregular GPGPU Applications. SC 2014: 128-139 - [e2]Rajeev Balasubramonian, Al Davis, Sarita V. Adve:
Architectural Support for Programming Languages and Operating Systems, ASPLOS 2014, Salt Lake City, UT, USA, March 1-5, 2014. ACM 2014, ISBN 978-1-4503-2305-5 [contents] - 2013
- [c36]Kshitij Sudan, Saisanthosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, Rajeev Balasubramonian:
A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O. HPCA 2013: 167-178 - [c35]Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Aniruddha N. Udipi:
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device. MICRO 2013: 198-209 - 2012
- [j9]Manu Awasthi, David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis:
Managing Data Placement in Memory Systems with Multiple Memory Controllers. Int. J. Parallel Program. 40(1): 57-83 (2012) - [c34]Kshitij Sudan, Sadagopan Srinivasan, Rajeev Balasubramonian, Ravi R. Iyer:
Optimizing datacenter power with memory system levers for guaranteed quality-of-service. PACT 2012: 117-126 - [c33]Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran
, Rajeev Balasubramonian, Viji Srinivasan:
Efficient scrub mechanisms for error-prone emerging memories. HPCA 2012: 15-26 - [c32]Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. HPCA 2012: 41-52 - [c31]Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. ISCA 2012: 285-296 - [c30]Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi R. Iyer:
Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access. MICRO 2012: 13-24 - [e1]Rajeev Balasubramonian, Vijayalakshmi Srinivasan:
2012 IEEE International Symposium on Performance Analysis of Systems & Software, New Brunswick, NJ, USA, April 1-3, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-1143-4 [contents] - 2011
- [b1]Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar:
Multi-Core Cache Hierarchies. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2011, ISBN 978-3-031-00606-7 - [j8]Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar R. Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian:
CHOP: Integrating DRAM Caches for CMP Server Platforms. IEEE Micro 31(1): 99-108 (2011) - [c29]Gagandeep S. Sachdev, Kshitij Sudan, Mary W. Hall
, Rajeev Balasubramonian:
Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures. PACT 2011: 175-176 - [c28]Manu Awasthi, David W. Nellans, Rajeev Balasubramonian, Al Davis:
Prediction Based DRAM Row-Buffer Management in the Many-Core Era. PACT 2011: 183-184 - [c27]Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. ISCA 2011: 425-436 - [r1]Rajeev Balasubramonian, Timothy Mark Pinkston:
Buses and Crossbars. Encyclopedia of Parallel Computing 2011: 200-205 - 2010
- [c26]Manu Awasthi, David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis:
Handling the problems and opportunities posed by multiple on-chip memory controllers. PACT 2010: 319-330 - [c25]Seth H. Pugsley, Josef B. Spjut, David W. Nellans, Rajeev Balasubramonian:
SWEL: hardware cache coherence protocols to map shared data onto shared caches. PACT 2010: 465-476 - [c24]Kshitij Sudan, Niladrish Chatterjee, David W. Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis:
Micro-pages: increasing DRAM efficiency with locality-aware data placement. ASPLOS 2010: 219-230 - [c23]Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar R. Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian:
CHOP: Adaptive filter-based DRAM caching for CMP server platforms. HPCA 2010: 1-12 - [c22]Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian:
Towards scalable, energy-efficient, bus-based on-chip networks. HPCA 2010: 1-12 - [c21]Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Rethinking DRAM design and organization for energy-constrained multi-cores. ISCA 2010: 175-186 - [c20]David W. Nellans, Kshitij Sudan, Erik Brunvand, Rajeev Balasubramonian:
Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality. ISCA Workshops 2010: 275-292 - [c19]David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Erik Brunvand:
Hardware prediction of OS run-length for fine-grained resource customization. ISPASS 2010: 111-112
2000 – 2009
- 2009
- [j7]David W. Nellans, Rajeev Balasubramonian, Erik Brunvand:
OS execution on multi-cores: is out-sourcing worthwhile? ACM SIGOPS Oper. Syst. Rev. 43(2): 104-105 (2009) - [c18]Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian:
Non-uniform power access in large caches with low-swing wires. HiPC 2009: 59-68 - [c17]Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter:
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches. HPCA 2009: 250-261 - [c16]Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell:
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. HPCA 2009: 262-274 - 2008
- [j6]Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi:
Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro 28(1): 69-79 (2008) - [c15]Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian:
Scalable and reliable communication for hardware transactional memory. PACT 2008: 144-154 - 2007
- [j5]Manu Awasthi, Vivek Venkatesan, Rajeev Balasubramonian:
Understanding the Impact of 3D Stacked Layouts on ILP. J. Instr. Level Parallelism 9 (2007) - [j4]Niti Madan, Rajeev Balasubramonian:
Power Efficient Approaches to Redundant Multithreading. IEEE Trans. Parallel Distributed Syst. 18(8): 1066-1079 (2007) - [c14]Naveen Muralimanohar, Rajeev Balasubramonian:
Interconnect design considerations for large NUCA caches. ISCA 2007: 369-380 - [c13]Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi:
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. MICRO 2007: 3-14 - [c12]Niti Madan, Rajeev Balasubramonian:
Leveraging 3D Technology for Improved Reliability. MICRO 2007: 223-235 - 2006
- [j3]Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter:
Leveraging Wire Properties at the Microarchitecture Level. IEEE Micro 26(6): 40-52 (2006) - [c11]Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter:
Interconnect-Aware Coherence Protocols for Chip Multiprocessors. ISCA 2006: 339-351 - [c10]Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian:
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. ISPASS 2006: 100-111 - 2005
- [c9]Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy:
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. HPCA 2005: 28-39 - 2004
- [c8]Rajeev Balasubramonian:
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures. ICS 2004: 326-335 - 2003
- [j2]David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas
, Eby G. Friedman, Michael C. Huang
, Volkan Kursun
, Grigorios Magklis, Michael L. Scott
, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster:
Dynamically Tuning Processor Resources with Adaptive Processing. Computer 36(12): 49-58 (2003) - [j1]Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
:
A Dynamically Tunable Memory Hierarchy. IEEE Trans. Computers 52(10): 1243-1258 (2003) - [c7]Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi:
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. ISCA 2003: 275-286 - [c6]Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu:
Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. PACS 2003: 180-195 - 2002
- [c5]Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas
, Greg Semeraro, Grigorios Magklis, Michael L. Scott
:
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. IEEE PACT 2002: 141-152 - [c4]Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas
, Michael L. Scott
:
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. HPCA 2002: 29-42 - 2001
- [c3]Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi:
Dynamically allocating processor resources between nearby and distant ILP. ISCA 2001: 26-37 - [c2]Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi:
Reducing the complexity of the register file in dynamic superscalar processors. MICRO 2001: 237-248 - 2000
- [c1]Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
:
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. MICRO 2000: 245-257
Coauthor Index
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