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Luca Bertulessi
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- affiliation: Polytechnic University of Milan, Italy
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2020 – today
- 2024
- [j12]Gabriele Zanoletti
, Lorenzo Scaletti
, Gabriele Bè
, Luca Ricci
, Michele Rocco
, Luca Bertulessi
, Carlo Samori
, Andrea Bonfanti
:
A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1551-1555 (2024) - 2023
- [j11]Francesco Buccoleri
, Simone Mattia Dartizio
, Francesco Tesolin
, Luca Avallone
, Alessio Santiccioli
, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. IEEE J. Solid State Circuits 58(3): 634-646 (2023) - [j10]Francesco Tesolin
, Simone Mattia Dartizio
, Francesco Buccoleri
, Alessio Santiccioli
, Luca Bertulessi
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays. IEEE J. Solid State Circuits 58(9): 2466-2477 (2023) - [c17]Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson, Dmytro Cherniak, Luca Bertulessi
, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. ISSCC 2023: 78-79 - [c16]Giacomo Castoro, Simone Mattia Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi
, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. ISSCC 2023: 82-83 - [c15]Lorenzo Scaletti, Luca Bertulessi
, Andrea Cristofoli, Andrea Bonfanti:
A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity. NEWCAS 2023: 1-5 - [c14]Luca Ricci, Lorenzo Scaletti
, Gabriele Bè
, Michele Rocco, Luca Bertulessi
, Salvatore Levantino, Andrea L. Lacaita, Carlo Samori, Andrea Bonfanti:
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j9]Mario Mercandelli
, Alessio Santiccioli
, Angelo Parisi
, Luca Bertulessi
, Dmytro Cherniak, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. IEEE J. Solid State Circuits 57(2): 505-517 (2022) - [j8]Simone Mattia Dartizio
, Francesco Tesolin
, Mario Mercandelli
, Alessio Santiccioli
, Abanob Shehata
, Saleh Karman
, Luca Bertulessi
, Francesco Buccoleri
, Luca Avallone
, Angelo Parisi
, Andrea L. Lacaita
, Michael Peter Kennedy
, Carlo Samori
, Salvatore Levantino
:
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. IEEE J. Solid State Circuits 57(6): 1723-1735 (2022) - [j7]Simone Mattia Dartizio
, Francesco Buccoleri
, Francesco Tesolin
, Luca Avallone
, Alessio Santiccioli
, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. IEEE J. Solid State Circuits 57(12): 3538-3551 (2022) - [j6]Luca Bertulessi
, Dmytro Cherniak
, Mario Mercandelli
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 1858-1870 (2022) - [j5]Gabriele Bè
, Angelo Parisi
, Luca Bertulessi
, Luca Ricci, Lorenzo Scaletti
, Mario Mercandelli
, Andrea L. Lacaita
, Salvatore Levantino
, Carlo Samori
, Andrea Bonfanti
:
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3645-3649 (2022) - [c13]Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
, Giovanni Steffan, Andrea Bevilacqua
, Luca Bertulessi
, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. CICC 2022: 1-2 - [c12]Luca Ricci, Lorenzo Scaletti
, Gabriele Bè
, Luca Bertulessi
, Salvatore Levantino, Carlo Samori, Andrea Bonfanti:
Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs. ISCAS 2022: 900-904 - [c11]Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino:
A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. ISSCC 2022: 1-3 - [c10]Lorenzo Scaletti
, Gabriele Bè
, Angelo Parisi, Luca Bertulessi
, Luca Ricci, Mario Mercandelli, Salvatore Levantino, Carlo Samori, Andrea Bonfanti:
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters. NEWCAS 2022: 20-24 - 2021
- [c9]Mario Mercandelli, Luca Bertulessi
, Carlo Samori, Salvatore Levantino:
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter. A-SSCC 2021: 1-3 - [c8]Carlo Samori, Luca Bertulessi
:
Digital PLLs: the modern timing reference for radar and communication systems. ESSCIRC 2021: 21-27 - [c7]Mario Mercandelli
, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata
, Francesco Tesolin, Saleh Karman, Luca Bertulessi
, Francesco Buccoleri, Luca Avallone, Angelo Parisi
, Andrea Leonardo Lacaita
, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. ISSCC 2021: 445-447 - [c6]Alessio Santiccioli, Mario Mercandelli
, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata
, Luca Bertulessi
, Francesco Buccoleri, Luca Avallone, Angelo Parisi
, Dmytro Cherniak, Andrea L. Lacaita
, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. ISSCC 2021: 456-458 - 2020
- [b1]Luca Bertulessi:
Frequency synthesizers based on PLLs for cellular radio applications. Polytechnic University of Milan, Italy, 2020 - [j4]Alessio Santiccioli
, Mario Mercandelli
, Luca Bertulessi
, Angelo Parisi
, Dmytro Cherniak, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. IEEE J. Solid State Circuits 55(12): 3349-3361 (2020) - [c5]Alessio Santiccioli, Mario Mercandelli
, Luca Bertulessi
, Angelo Parisi
, Dmytro Cherniak, Andrea Leonardo Lacaita
, Carlo Samori, Salvatore Levantino:
17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. ISSCC 2020: 268-270 - [c4]Mario Mercandelli
, Alessio Santiccioli, Angelo Parisi
, Luca Bertulessi
, Dmytro Cherniak, Andrea Leonardo Lacaita
, Carlo Samori, Salvatore Levantino:
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. ISSCC 2020: 274-276
2010 – 2019
- 2019
- [j3]Luca Bertulessi
, Saleh Karman
, Dmytro Cherniak, Alessandro Garghetti
, Carlo Samori, Andrea L. Lacaita
, Salvatore Levantino
:
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. IEEE J. Solid State Circuits 54(12): 3493-3502 (2019) - [c3]Luigi Grimaldi, Luca Bertulessi
, Saleh Karman
, Dmytro Cherniak, Alessandro Garghetti
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino:
A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. ISSCC 2019: 268-270 - 2018
- [j2]Mario Mercandelli
, Luigi Grimaldi
, Luca Bertulessi
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Background Calibration Technique to Control the Bandwidth of Digital PLLs. IEEE J. Solid State Circuits 53(11): 3243-3255 (2018) - [j1]Dmytro Cherniak
, Luigi Grimaldi
, Luca Bertulessi
, Roberto Nonis, Carlo Samori
, Salvatore Levantino
:
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation. IEEE J. Solid State Circuits 53(12): 3565-3575 (2018) - [c2]Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi
, Carlo Samori
, Roberto Nonis, Salvatore Levantino
:
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. ISSCC 2018: 248-250 - [c1]Luca Bertulessi
, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori
, Salvatore Levantino
:
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range. ISSCC 2018: 252-254
Coauthor Index
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last updated on 2024-05-08 21:02 CEST by the dblp team
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