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Sneh Saurabh
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2020 – today
- 2024
- [c13]Shivendra Singh, Ekta Tiwari, Abhinav Gupta, Sneh Saurabh:
Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis. VLSID 2024: 25-30 - [c12]Pranav Jain, Gagandeep, Sneh Saurabh:
FLIP: An Artificial Neural Network-based Post-routing Incremental Placer. VLSID 2024: 55-60 - [c11]Pooja Beniwal, Sneh Saurabh:
Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement. VLSID 2024: 300-305 - 2023
- [j7]Syed Asrar ul Haq
, Abdul Karim Gizzini
, Shakti Shrey, Sumit Jagdish Darak
, Sneh Saurabh
, Marwa Chafii
:
Deep Neural Network Augmented Wireless Channel Estimation for Preamble-Based OFDM PHY on Zynq System on Chip. IEEE Trans. Very Large Scale Integr. Syst. 31(7): 1026-1038 (2023) - [c10]Amina Haroon, Ram Krishna Ghosh, Sneh Saurabh:
Implementation of Probabilistic Bits (Pbits) using Low Barrier Magnets: Investigation and Analysis. VLSID 2023: 307-312 - 2022
- [j6]Jasmine Kaur, Sneh Saurabh
, Shubham Sahay
:
Muller C-Element Exploiting Programmable Metallization Cell for Bayesian Inference. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 750-761 (2022) - [c9]Raiyyan Malik, Shubham Baunthiyal, Puneet Kumar, Srinath J, Sneh Saurabh:
A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking. VLSI-SoC 2022: 1-6 - [c8]Amina Haroon, Sneh Saurabh:
Image Completion using a Sparse Probabilistic Spin Logic Network. VLSID 2022: 281-286 - [d1]Sneh Saurabh, Rajat Kumar:
Characterization Data for Flip-flop. IEEE DataPort, 2022 - [i1]Syed Asrar ul Haq, Abdul Karim Gizzini, Shakti Shrey, Sumit Jagdish Darak, Sneh Saurabh, Marwa Chafii:
Deep Neural Network Augmented Wireless Channel Estimation on System on Chip. CoRR abs/2209.02213 (2022) - 2021
- [j5]Mamidala Karthik Ram
, Neha Tiwari
, Dawit Burusie Abdi
, Sneh Saurabh
:
Effect of Drain Induced Barrier Enhancement on Subthreshold Swing and OFF-State Current of Short Channel MOSFETs: A TCAD Study. IEEE Access 9: 141321-141328 (2021) - [j4]Mamidala Karthik Ram
, Neha Tiwari
, Dawit Burusie Abdi
, Sneh Saurabh
:
Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis. IEEE Access 9: 150366-150372 (2021) - [j3]O. V. S. Shashank Ram
, Sneh Saurabh
:
Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 723-734 (2021) - [c7]Madhvi Agarwal, Sneh Saurabh:
An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network. MLCAD 2021: 1-6 - [c6]Akshay Balaji, Sneh Saurabh:
Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate-Source Underlap. VLSI-SoC 2021: 1-6 - 2020
- [c5]Subhadip Poria, Shelly Garg, Sneh Saurabh
:
Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate. VDAT 2020: 1-6
2010 – 2019
- 2019
- [j2]Akhil James, Sneh Saurabh
:
Dopingless 1T DRAM: Proposal, Design, and Analysis. IEEE Access 7: 88960-88969 (2019) - [j1]Shelly Garg
, Sneh Saurabh
:
Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis. IEEE Access 7: 117591-117599 (2019) - [c4]Vaibhav Agarwal, Sneh Saurabh
:
Application of Probabilistic Spin Logic (PSL) in Detecting Satisfiability of a Boolean Function. ISQED 2019: 70-75 - [c3]Vaibhav Agarwal, Sneh Saurabh
:
Realizing Boolean Functions Using Probabilistic Spin Logic (PSL). VLSID 2019: 508-509 - 2018
- [c2]Sneh Saurabh
, Vishav Vikash:
Assessing the Impact of Temperature and Supply Voltage Variations in Near-threshold Circuits using an Analytical Model. ACM Great Lakes Symposium on VLSI 2018: 93-98 - [c1]Sneh Saurabh
, Priyanka Mittal:
A Practical Methodology to Compress Technology Libraries Using Recursive Polynomial Representation. VLSID 2018: 301-306
Coauthor Index
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last updated on 2024-06-19 20:58 CEST by the dblp team
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