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ORCIDYufei Ma 0002
Person information
- affiliation: Peking University, Beijing, China
- affiliation (former): Arizona State University, Tempe, AZ, USA
Other persons with the same name
- Yufei Ma 0001
![[0000-0002-9788-7984]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-9788-7984")
— Harbin Institute of Technology, National Key Laboratory of Science and Technology on Tunable Laser, China - Yufei Ma 0003 — Beijing Jiaotong University, China
- Yufei Ma 0004 — South China University of Technology, Guangzhou, China
- Yufei Ma 0005 — Northwest University, Xi'an, Shaanxi, China
- Yufei Ma 0006 — Microsoft Research Asia, Beijing, China
- Yufei Ma 0007 — IBM China Research Lab, Beijing, China
- Yufei Ma 0008 — Nanjing University of Information Science and Technology, Nanjing, China
- Yufei Ma 0009 — China Research Laboratory, China
- Yufei Ma 0010 — University of Glasgow, Centre for Advance Electronics, UK
- Yufei Ma 0011 — Northwestern Polytechnical University, Xi'an, China
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2020 – today
- 2024
[j11]Ying Liu, Zhiyuan Chen, Wentao Zhao, Tianhao Zhao, Tianyu Jia, Zhixuan Wang, Ru Huang, Le Ye, Yufei Ma:
Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2660-2673 (2024)- [j10]Yufei Ma, Yikan Qiu, Wentao Zhao, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang:
DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2735-2748 (2024) - [c24]Yikan Qiu, Yufei Ma, Meng Wu, Yifan Jia, Xinyu Qu, Zecheng Zhou, Jincheng Lou, Tianyu Jia, Le Ye, Ru Huang:
Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow. CICC 2024: 1-2 - [c23]Meng Wu, Wenjie Ren, Peiyu Chen, Wentao Zhao, Yiqi Jing, Jiayoon Ru, Zhixuan Wang, Yufei Ma, Ru Huang, Tianyu Jia, Le Ye:
S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications. CICC 2024: 1-2 - [c22]Ying Liu, Yufei Ma, Ninghui Shang, Tianhao Zhao, Peiyu Chen, Meng Wu, Jiayoon Ru, Tianyu Jia, Le Ye, Zhixuan Wang, Ru Huang:
30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing. ISSCC 2024: 484-486 - [c21]Yanchi Dong, Xueping Liu, Kangbo Bai, Guoxiang Li, Meng Wu, Yiqi Jing, Yihan Zhang, Pixian Zhan, Yadong Zhang, Yufei Ma, Ru Huang, Le Ye, Tianyu Jia:
A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup. VLSI Technology and Circuits 2024: 1-2 - [i3]Xu Zhu, Yufei Ma, Xiaoguang Li, Tiejun Li:
Alternating Subspace Approximate Message Passing. CoRR abs/2407.07436 (2024) - 2023
- [j9]Le Ye, Zhixuan Wang, Tianyu Jia, Yufei Ma, Linxiao Shen, Yihan Zhang, Heyi Li, Peiyu Chen, Meng Wu, Ying Liu, Yiqi Jing, Hao Zhang, Ru Huang:
Research progress on low-power artificial intelligence of things (AIoT) chip design. Sci. China Inf. Sci. 66(10) (2023) - [j8]Ying Liu, Yufei Ma, Wei He, Zhixuan Wang, Linxiao Shen, Jiayoon Ru, Ru Huang, Le Ye:
An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3075-3088 (2023) - [c20]Peiyu Chen, Meng Wu, Yufei Ma, Le Ye, Ru Huang:
RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation. ASP-DAC 2023: 228-233 - [c19]Ying Liu, Zhiyuan Chen, Zhixuan Wang, Wentao Zhao, Wei He, Jianfeng Zhu, Oijun Wang, Ning Zhang, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang:
A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology. CICC 2023: 1-2 - [c18]Yanchi Dong, Tianyu Jia, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Yadong Zhang, Fengyun Yan, Yufei Ma, Yun Liang, Le Ye, Ru Huang:
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware. DAC 2023: 1-6 - [c17]Yiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma, Le Ye, Tianyu Jia:
DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler. ISLPED 2023: 1-6 - [c16]Peiyu Chen, Meng Wu, Wentao Zhao, Jiajia Cui, Zhixuan Wang, Yadong Zhang, Qijun Wang, Jiayoon Ru, Linxiao Shen, Tianyu Jia, Yufei Ma, Le Ye, Ru Huang:
A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. ISSCC 2023: 140-141 - 2022
- [j7]Xiao Wu, Yufei Ma, Meiqi Wang, Zhongfeng Wang:
A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1185-1198 (2022) - [j6]Zhiyuan Chen, Yufei Ma, Zhongfeng Wang:
Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2707-2720 (2022) - [c15]Yikan Qiu, Yufei Ma, Wentao Zhao, Meng Wu, Le Ye, Ru Huang:
DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks. ICCAD 2022: 46:1-46:9 - 2021
- [c14]Yufei Ma, Gokul Krishnan, Yu Cao, Le Ye, Ru Huang:
SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA. FPGA 2021: 148 - 2020
- [j5]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo:
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 424-437 (2020) - [j4]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo:
Performance Modeling for CNN Inference Accelerators on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 843-856 (2020) - [c13]Jiayu Wen, Yufei Ma, Zhongfeng Wang:
An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference. APCCAS 2020: 165-168 - [c12]Yufei Ma, Yuan Du, Li Du, Jun Lin, Zhongfeng Wang:
In-Memory Computing: The Next-Generation AI Computing Paradigm. ACM Great Lakes Symposium on VLSI 2020: 265-270 - [c11]Zhiyuan Chen, Yufei Ma, Zhongfeng Wang:
Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks. ICCAD 2020: 90:1-90:7 - [c10]Hui Zhang, Wei Wu, Yufei Ma, Zhongfeng Wang:
Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGA. ISVLSI 2020: 580-585 - [c9]Xiao Wu, Yufei Ma, Zhongfeng Wang:
Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA. SoCC 2020: 168-173
2010 – 2019
- 2019
- [j3]Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao:
Efficient Network Construction Through Structural Plasticity. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 453-464 (2019) - [c8]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. FPL 2019: 166-172 - [i2]Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao:
Efficient Network Construction through Structural Plasticity. CoRR abs/1905.11530 (2019) - [i1]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR abs/1908.06724 (2019) - 2018
- [b1]Yufei Ma:
Hardware Acceleration of Deep Convolutional Neural Networks on FPGA. Arizona State University, Tempe, USA, 2018 - [j2]Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. 62: 14-23 (2018) - [j1]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1354-1367 (2018) - [c7]Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. ICCAD 2018: 57 - 2017
- [c6]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA 2017: 45-54 - [c5]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. FPL 2017: 1-8 - [c4]Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
End-to-end scalable FPGA accelerator for deep residual networks. ISCAS 2017: 1-4 - 2016
- [c3]Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA 2016: 16-25 - [c2]Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL 2016: 1-8 - 2015
- [c1]Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. ICCD 2015: 443-446
Coauthor Index
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