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ORCIDThomas R. Shiple
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2010 – 2019
- 2012
[j3]Michael Mendler, Thomas R. Shiple, Gérard Berry:
Constructive Boolean circuits and the exactness of timed ternary simulation. Formal Methods Syst. Des. 40(3): 283-329 (2012)- 2011
- [c22]Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho:
Multi-mode redundancy removal. ISQED 2011: 791-799
2000 – 2009
- 2002
- [j2]Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
:
Formula-Dependent Equivalence for Compositional CTL Model Checking. Formal Methods Syst. Des. 21(2): 193-224 (2002) - [c21]In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley:
Simplifying Circuits for Formal Verification Using Parametric Representation. FMCAD 2002: 52-69 - [c20]Hee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple:
Combinational equivalence checking through function transformation. ICCAD 2002: 526-533 - 2001
- [j1]Adnan Aziz, James H. Kukula, Thomas R. Shiple, Jun Yuan:
Efficient control state-space search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 332-336 (2001) - [c19]Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Thomas R. Shiple, Helmut Veith, Dong Wang:
Non-linear Quantification Scheduling in Image Computation. ICCAD 2001: 293- - 2000
- [c18]James H. Kukula, Thomas R. Shiple:
Building Circuits from Relations. CAV 2000: 113-123 - [c17]Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long:
Smart Simulation Using Collaborative Formal and Simulation Engines. ICCAD 2000: 120-126
1990 – 1999
- 1999
- [c16]In-Ho Moon, James H. Kukula, Thomas R. Shiple, Fabio Somenzi:
Least fixpoint approximations for reachability analysis. ICCAD 1999: 41-44 - 1998
- [c15]Thomas R. Shiple, James H. Kukula, Rajeev K. Ranjan:
A Comparison of Presburger Engines for EFSM Reachability. CAV 1998: 280-292 - [c14]Kavita Ravi, Kenneth L. McMillan, Thomas R. Shiple, Fabio Somenzi:
Approximation and Decomposition of Binary Decision Diagrams. DAC 1998: 445-450 - [c13]Adnan Aziz, James H. Kukula, Thomas R. Shiple:
Hybrid Verification Using Saturated Simulation. DAC 1998: 615-618 - [c12]James H. Kukula, Thomas R. Shiple, Adnan Aziz:
Techniques for Implicit State Enumeration of EFSMs. FMCAD 1998: 469-482 - 1996
- [c11]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS: A System for Verification and Synthesis. CAV 1996: 428-432 - [c10]Thomas R. Shiple, Gérard Berry, Hervé J. Touati:
Constructive Analysis of Cyclic Circuits. ED&TC 1996: 328-333 - [c9]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS. FMCAD 1996: 248-256 - 1994
- [c8]Adnan Aziz, Thomas R. Shiple, Vigyan Singhal:
Formula-Dependent Equivalence for Compositional CTL Model Checking. CAV 1994: 324-337 - [c7]Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton:
Heuristic Minimization of BDDs Using Don't Cares. DAC 1994: 225-231 - [c6]Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459 - [c5]Kevin Covey, Sandra Murdock, Thomas R. Shiple:
Two-phase Logic Design by Hardware Flowcharts. ICCD 1994: 368-380 - 1993
- [c4]Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan:
A Unified Approach to Language Containment and Fair CTL Model Checking. DAC 1993: 475-481 - 1992
- [c3]Thomas R. Shiple, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton:
Automatic Reduction in CTL Compositional Model Checking. CAV 1992: 234-247 - [c2]Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton:
Automatic compositional minimization in CTL model checking. ICCAD 1992: 172-178
1980 – 1989
- 1989
- [c1]Antun Domic, Samuel Levitin, Nathan Phillips, Channeary Thai, Thomas R. Shiple, Dilip Bhavsar, Clint Bissel:
CLEO: a CMOS layout generator. ICCAD 1989: 340-343
Coauthor Index
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