30th DAC 1993: Dallas, Texas, USA

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Asynchronous Circuit Design

Sequential Circuit Analysis and Optimization

Fast Algorithm for Layout Analysis

Increasing Design Quality and Engineering Productivity through Design Reuse

New Ideas in Technology Mapping

Test Generation

Timing Estimation and Verification


Optimization of Analog Circuits


Optimal Tree Construction

High Level Design Implementation

Technology Mapping for FPGAS and Layout

Design for Test

Extending the Applicability of BDDs

Information Modeling


System Implementation Issues


FPGA Layout and Partitioning

EDAC User Session

DSP Synthesis

Simulation and Analysis of Digital Circuits

Large-Scale Compaction

Issues in System Design

Testing of Delay and Bridging Faults

Formal Verification


Retiming and Timing Analysis in Sequential Synthesis

Fault Simulation and Diagnosis

Placement and Floorplanning

Practical Design and Validation Techniques

Retiming and Scheduling


Performance-Driven Routing


Advances in Logic Synthesis

Infrastructure from Process to Debugging

High Speed Interconnects Analysis

Russian CAE