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2010 – 2019
- 2018
[j9]Eric Cheng
, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1839-1852 (2018)- 2017
- [j8]Hyungmin Cho, Eric Cheng, Thomas Shepherd, Chen-Yong Cher, Subhasish Mitra:
System-Level Effects of Soft Errors in Uncore Components. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1497-1510 (2017) - [c33]Karthik Swaminathan, Nandhini Chandramoorthy, Chen-Yong Cher, Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose:
BRAVO: Balanced Reliability-Aware Voltage Optimization. HPCA 2017: 97-108 - [c32]Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra:
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. ICCD 2017: 593-596 - [i3]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). CoRR abs/1709.09921 (2017) - 2016
- [c31]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores. DAC 2016: 68:1-68:6 - [c30]William J. Song, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose:
Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency. ISLPED 2016: 284-289 - [c29]Guanpeng Li, Karthik Pattabiraman, Chen-Yong Cher, Pradip Bose:
Understanding error propagation in GPGPU applications. SC 2016: 240-251 - [i2]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores. CoRR abs/1604.03062 (2016) - 2015
- [j7]Ravi Nair, Samuel Antão, Carlo Bertolli, Pradip Bose, José R. Brunheroto, Tong Chen, Chen-Yong Cher, Carlos H. A. Costa, J. Doi, Constantinos Evangelinos, Bruce M. Fleischer, Thomas W. Fox, Diego S. Gallo, Leopold Grinberg, John A. Gunnels, Arpith C. Jacob, P. Jacob, Hans M. Jacobson, Tejas Karkhanis, C. Kim, Jaime H. Moreno, John K. O'Brien, Martin Ohmacht, Yoonho Park, Daniel A. Prener, Bryan S. Rosenburg, Kyung Dong Ryu, Olivier Sallenave, Mauricio J. Serrano, P. D. M. Siegl, Krishnan Sugavanam, Zehra Sura:
Active Memory Cube: A processing-in-memory architecture for exascale systems. IBM J. Res. Dev. 59(2/3) (2015) - [c28]Hyungmin Cho, Chen-Yong Cher, Thomas Shepherd, Subhasish Mitra:
Understanding soft errors in uncore components. DAC 2015: 89:1-89:6 - [c27]Shahrzad Mirkhani, Subhasish Mitra, Chen-Yong Cher, Jacob A. Abraham:
Efficient soft error vulnerability estimation of complex designs. DATE 2015: 103-108 - [c26]Guanpeng Li, Karthik Pattabiraman, Chen-Yong Cher, Pradip Bose:
Experience report: An application-specific checkpointing technique for minimizing checkpoint corruption. ISSRE 2015: 141-152 - [c25]Rizwan A. Ashraf, Roberto Gioiosa, Gokcen Kestor, Ronald F. DeMara, Chen-Yong Cher, Pradip Bose:
Understanding the propagation of transient errors in HPC applications. SC 2015: 72:1-72:12 - [i1]Hyungmin Cho, Chen-Yong Cher, Thomas Shepherd, Subhasish Mitra:
Understanding Soft Errors in Uncore Components. CoRR abs/1504.01381 (2015) - 2014
- [c24]Chen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas Gooding, Kristan D. Davis, Marc Boris Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam:
Soft Error Resiliency Characterization on IBM BlueGene/Q Processor. ASP-DAC 2014: 385-387 - [c23]Vikas Chandra, Subhasish Mitra, Chen-Yong Cher, Silvia Melitta Müller:
Cross layer resiliency in real world. DATE 2014: 1 - [c22]Chen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas Gooding, Kristan D. Davis, Marc Boris Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam:
Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation. ITC 2014: 1-6 - [c21]Chen-Yong Cher, Meeta Sharma Gupta, Pradip Bose, K. Paul Muller:
Understanding Soft Error Resiliency of Blue Gene/Q Compute Chip through Hardware Proton Irradiation and Software Fault Injection. SC 2014: 587-596 - [c20]Carlos H. A. Costa, Yoonho Park, Bryan S. Rosenburg, Chen-Yong Cher, Kyung Dong Ryu:
A System Software Approach to Proactive Memory-Error Avoidance. SC 2014: 707-718 - [c19]Subhasish Mitra, Pradip Bose, Eric Cheng, Chen-Yong Cher, Hyungmin Cho, Rajiv V. Joshi, Young Moon Kim, Charles R. Lefurgy, Yanjing Li, Kenneth P. Rodbell, Kevin Skadron, James H. Stathis, Lukasz G. Szafaryn:
The resilience wall: Cross-layer solution strategies. VLSI-DAT 2014: 1-11 - 2013
- [j6]Krishnan Sugavanam, Chen-Yong Cher, John A. Gunnels, Ruud A. Haring, Philip Heidelberger, Hans M. Jacobson, Moyra K. McManus, D. P. Paulsen, David L. Satterfield, Yutaka Sugawara, Robert Walkup:
Design for low power and power management in IBM Blue Gene/Q. IBM J. Res. Dev. 57(1/2): 3 (2013) - [j5]Alessandro Morari, Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Trans. Computers 62(4): 813-826 (2013) - [c18]Hyungmin Cho, Shahrzad Mirkhani, Chen-Yong Cher, Jacob A. Abraham, Subhasish Mitra:
Quantitative evaluation of soft error injection techniques for robust system design. DAC 2013: 101:1-101:10 - [c17]Chen-Yong Cher, Mohan J. Kumar:
Innovative practices session 11C: Resilience. VTS 2013: 1 - [c16]Chen-Yong Cher, Yiorgos Makris, C. Thibeault, Alan J. Drake:
Innovative practices session 7C: Self-calibration & trimming. VTS 2013: 1 - 2012
- [c15]Huapeng Zhou, Xin Li, Chen-Yong Cher, Eren Kursun, Haifeng Qian, Shi-Chune Yao:
An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring. DAC 2012: 642-647 - 2011
- [j4]Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose:
Characterizing Power and Temperature Behavior of POWER6-Based System. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 228-241 (2011) - [j3]Chen-Yong Cher, Eren Kursun:
Exploring the effects of on-chip thermal variation on high-performance multicore architectures. ACM Trans. Archit. Code Optim. 8(1): 2:1-2:22 (2011) - 2010
- [c14]Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose:
Power and thermal characterization of POWER6 system. PACT 2010: 7-18 - [c13]Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose:
Performance and power evaluation of an in-line accelerator. Conf. Computing Frontiers 2010: 81-82 - [c12]Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban:
Power-efficient, reliable microprocessor architectures: modeling and design methods. ACM Great Lakes Symposium on VLSI 2010: 299-304 - [c11]Charles L. Johnson, David H. Allen, Jeffrey D. Brown, Steve Vanderwiel, Russ Hoover, Heather D. Achilles, Chen-Yong Cher, George A. May, Hubertus Franke, Jimi Xenidis, Claude Basso:
A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads. ISSCC 2010: 104-105 - [c10]Víctor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
Trends and techniques for energy efficient architectures. VLSI-SoC 2010: 276-279
2000 – 2009
- 2009
- [j2]Eren Kursun, Chen-Yong Cher:
Temperature Variation Characterization and Thermal Management of Multicore Architectures. IEEE Micro 29(1): 116-126 (2009) - 2008
- [c9]Eren Kursun, Chen-Yong Cher:
Variation-aware thermal characterization and management of multi-core architectures. ICCD 2008: 280-285 - [c8]Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero:
Software-Controlled Priority Characterization of POWER5 Processor. ISCA 2008: 415-426 - [c7]Chen-Yong Cher, Michael Gschwind:
Cell GC: using the cell synergistic processor as a garbage collection coprocessor. VEE 2008: 141-150 - 2007
- [c6]Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Hendrik F. Hamann, Alan J. Weger, Pradip Bose:
Thermal-aware task scheduling at the system software level. ISLPED 2007: 213-218 - 2006
- [c5]Chen-Yong Cher, Il Park, T. N. Vijaykumar:
Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?. ARCS 2006: 232-251 - [c4]Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi:
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. MICRO 2006: 347-358 - 2005
- [j1]Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar:
Combined circuit and architectural level variable supply-voltage scaling for low power. IEEE Trans. Very Large Scale Integr. Syst. 13(5): 564-576 (2005) - 2004
- [c3]Chen-Yong Cher, Antony L. Hosking, T. N. Vijaykumar:
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign. ASPLOS 2004: 199-210 - 2003
- [c2]Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy:
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. MICRO 2003: 19-28 - 2001
- [c1]Chen-Yong Cher, T. N. Vijaykumar:
Skipper: a microarchitecture for exploiting control-flow independence. MICRO 2001: 4-15
Coauthor Index
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