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2020 – today
- 2024
[j16]Reetuparna Das
, Satish Narayanasamy:
Systems Challenges and Opportunities for Genomics. Computer 57(8): 127-135 (2024)- [c62]Vidushi Goyal, Valeria Bertacco, Reetuparna Das:
Duet: A Collaborative User Driven Recommendation System for Edge Devices. DAC 2024: 55:1-55:6 - 2023
- [j15]Timothy Dunn, David T. Blaauw, Reetuparna Das, Satish Narayanasamy:
nPoRe: n-polymer realigner for improved pileup-based variant calling. BMC Bioinform. 24(1): 98 (2023) - [j14]Charles Eckert, Arun Subramaniyan, Xiaowei Wang, Charles Augustine, Ravishankar Iyer, Reetuparna Das:
Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks. IEEE Trans. Computers 72(6): 1539-1553 (2023) - [j13]Yunjie Pan, Jiecao Yu, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke:
BitSET: Bit-Serial Early Termination for Computation Reduction in Convolutional Neural Networks. ACM Trans. Embed. Comput. Syst. 22(5s): 98:1-98:24 (2023) - [c61]Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das:
Vector-Processing for Mobile Devices: Benchmark and Analysis. IISWC 2023: 15-27 - [c60]Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das:
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis. ISCA 2023: 25:1-25:15 - [i3]Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das:
Vector-Processing for Mobile Devices: Benchmark and Analysis. CoRR abs/2309.02680 (2023) - 2022
- [j12]Reetuparna Das:
Special Issue on In-Memory Computing. IEEE Micro 42(1): 87-88 (2022) - [j11]Vidushi Goyal, Reetuparna Das, Valeria Bertacco:
Hardware-friendly User-specific Machine Learning for Edge Devices. ACM Trans. Embed. Comput. Syst. 21(5): 62:1-62:29 (2022) - [c59]Daichi Fujiki, Alireza Khadem, Scott A. Mahlke, Reetuparna Das:
Multi-Layer In-Memory Processing. MICRO 2022: 920-936 - 2021
- [b1]Daichi Fujiki, Xiaowei Wang, Arun Subramaniyan, Reetuparna Das:
In-/Near-Memory Computing. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2021, ISBN 978-3-031-00644-9, pp. 1-140 - [j10]Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw:
A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array. IEEE J. Solid State Circuits 56(3): 824-833 (2021) - [c58]Vidushi Goyal, Valeria Bertacco, Reetuparna Das:
MyML: User-Driven Machine Learning. DAC 2021: 145-150 - [c57]Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das:
Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM 2021: 88-96 - [c56]Arun Subramaniyan, Jack Wadden, Kush Goliya, Nathan Ozog, Xiao Wu, Satish Narayanasamy, David T. Blaauw, Reetuparna Das:
Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees. ISCA 2021: 388-401 - [c55]Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das:
GenomicsBench: A Benchmark Suite for Genomics. ISPASS 2021: 1-12 - [c54]Timothy Dunn, Harisankar Sadasivan, Jack Wadden, Kush Goliya, Kuan-Yu Chen, David T. Blaauw, Reetuparna Das, Satish Narayanasamy:
SquiggleFilter: An Accelerator for Portable Virus Detection. MICRO 2021: 535-549 - [c53]Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi R. Iyer, Li Zhao, Reetuparna Das:
Cache Compression with Efficient in-SRAM Data Comparison. NAS 2021: 1-8 - 2020
- [j9]Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester:
A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing. IEEE J. Solid State Circuits 55(1): 76-86 (2020) - [c52]Yujun Qin, Samuel Gonzalez, Kevin Angstadt, Xiaowei Wang, Stephanie Forrest, Reetuparna Das, Kevin Leach, Westley Weimer:
MARTINI: Memory Access Traces to Detect Attacks. CCSW 2020: 77-90 - [c51]Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw:
A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array. CICC 2020: 1-4 - [c50]Vidushi Goyal, Valeria Bertacco, Reetuparna Das:
Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning. DAC 2020: 1-19 - [c49]Vidushi Goyal, Xiaowei Wang, Valeria Bertacco, Reetuparna Das:
Neksus: An Interconnect for Heterogeneous System-In-Package Architectures. IPDPS 2020: 12-21 - [c48]Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das:
SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space. MICRO 2020: 937-950 - [c47]Xiao Wu, Arun Subramaniyan, Zhehong Wang, Satish Narayanasamy, Reetu Das, David T. Blaauw:
17.3 GCUPS Pruning-Based Pair-Hidden-Markov-Model Accelerator for Next-Generation DNA Sequencing. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j8]Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Dennis Sylvester, David T. Blaauw, Reetuparna Das, Ravi R. Iyer:
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. IEEE Micro 39(3): 11-19 (2019) - [j7]Jiecao Yu, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke:
TF-Net: Deploying Sub-Byte Deep Neural Networks on Microcontrollers. ACM Trans. Embed. Comput. Syst. 18(5s): 45:1-45:21 (2019) - [c46]Xiaowei Wang, Jiecao Yu, Charles Augustine, Ravi R. Iyer, Reetuparna Das:
Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks. HPCA 2019: 81-93 - [c45]Daichi Fujiki, Scott A. Mahlke, Reetuparna Das:
Duality cache for data parallel acceleration. ISCA 2019: 397-410 - [c44]Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester:
A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration. ISSCC 2019: 224-226 - [c43]Reetu Das:
Compute cache for data parallel acceleration. NoCArc@MICRO 2019: 2:1 - 2018
- [c42]Daichi Fujiki, Scott A. Mahlke, Reetuparna Das:
In-Memory Data Parallel Processor. ASPLOS 2018: 1-14 - [c41]Daichi Fujiki, Arun Subramaniyan, Tianjun Zhang, Yu Zeng, Reetuparna Das, David T. Blaauw, Satish Narayanasamy:
GenAx: A Genome Sequencing Accelerator. ISCA 2018: 69-82 - [c40]Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi R. Iyer, Dennis Sylvester, David T. Blaauw, Reetuparna Das:
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. ISCA 2018: 383-396 - [c39]Kevin Angstadt, Arun Subramaniyan, Elaheh Sadredini, Reza Rahimi, Kevin Skadron, Westley Weimer, Reetuparna Das:
ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata. MICRO 2018: 921-932 - [i2]Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi R. Iyer, Dennis Sylvester, David T. Blaauw, Reetuparna Das:
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. CoRR abs/1805.03718 (2018) - 2017
- [j6]Reetuparna Das:
Blurring the Lines between Memory and Computation. IEEE Micro 37(6): 13-15 (2017) - [c38]Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das:
Cache Automaton: Repurposing Caches for Automata Processing. PACT 2017: 373 - [c37]Daichi Fujiki, Scott A. Mahlke, Reetuparna Das:
In-memory Data Flow Processor. PACT 2017: 375 - [c36]Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Reetuparna Das, Todd M. Austin:
Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors. HPCA 2017: 313-324 - [c35]Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David T. Blaauw, Reetuparna Das:
Compute Caches. HPCA 2017: 481-492 - [c34]Jiecao Yu, Andrew Lukefahr, David J. Palframan, Ganesh S. Dasika, Reetuparna Das, Scott A. Mahlke:
Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism. ISCA 2017: 548-560 - [c33]Arun Subramaniyan, Reetuparna Das:
Parallel Automata Processor. ISCA 2017: 600-612 - [c32]Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das:
Cache automaton. MICRO 2017: 259-272 - [c31]Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke:
Mirage cores: the illusion of many out-of-order cores using in-order hardware. MICRO 2017: 745-758 - 2016
- [j5]Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu:
A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate. Parallel Comput. 54: 29-45 (2016) - [j4]Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke:
Exploring Fine-Grained Heterogeneity with Composite Cores. IEEE Trans. Computers 65(2): 535-547 (2016) - [c30]Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Rui Qiao, Reetuparna Das, Matthew Hicks, Yossi Oren, Todd M. Austin:
ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. ASPLOS 2016: 743-755 - [c29]Salessawi Ferede Yitbarek, Tao Yang, Reetuparna Das, Todd M. Austin:
Exploring specialized near-memory processing for data intensive operations. DATE 2016: 1449-1452 - [i1]Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu:
Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing. CoRR abs/1602.06005 (2016) - 2015
- [c28]William Arthur, Ben Mehne, Reetuparna Das, Todd M. Austin:
Getting in control of your control flow with control-data isolation. CGO 2015: 79-90 - [c27]William Arthur, Sahil Madeka, Reetuparna Das, Todd M. Austin:
Locking down insecure indirection with hardware-based control-data isolation. MICRO 2015: 115-127 - [c26]Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke:
DynaMOS: dynamic schedule migration for heterogeneous cores. MICRO 2015: 322-333 - 2014
- [c25]Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke:
Heterogeneous microarchitectures trump voltage scaling for low-power cores. PACT 2014: 237-250 - [c24]Supriya Rao, Supreet Jeloka, Reetuparna Das, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge:
VIX: Virtual Input Crossbar for Efficient Switch Allocation. DAC 2014: 103:1-103:6 - [c23]Ritesh Parikh, Reetuparna Das, Valeria Bertacco:
Power-Aware NoCs through Routing and Topology Reconfiguration. DAC 2014: 162:1-162:6 - [c22]Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David T. Blaauw, Ronald G. Dreslinski, Reetuparna Das, Trevor N. Mudge:
Quality-of-Service for a High-Radix Switch. DAC 2014: 163:1-163:6 - [c21]Supreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, David T. Blaauw:
Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration. MICRO 2014: 471-483 - [c20]Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu:
Design and Evaluation of Hierarchical Rings with Deflection Routing. SBAC-PAD 2014: 230-237 - 2013
- [c19]Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi:
Application-to-core mapping policies to reduce memory system interference in multi-core systems. HPCA 2013: 107-118 - [c18]Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge:
Scaling towards kilo-core processors with asymmetric high-radix topologies. HPCA 2013: 496-507 - [c17]Reetuparna Das, Satish Narayanasamy, Sudhir Satpathy, Ronald G. Dreslinski:
Catnap: energy proportional multiple network-on-chip. ISCA 2013: 320-331 - [c16]Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke:
Trace based phase prediction for tightly-coupled heterogeneous cores. MICRO 2013: 445-456 - 2012
- [j3]Korey Sewell, Ronald G. Dreslinski, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge:
Swizzle-Switch Networks for Many-Core Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 278-294 (2012) - [c15]Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das, Nathaniel Ross Pinckney, Sudhir Satpathy, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge:
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems. PACT 2012: 75-86 - [c14]Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi:
Application-to-core mapping policies to reduce memory interference in multi-core systems. PACT 2012: 455-456 - [c13]Sudhir Satpathy, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service. DAC 2012: 406-411 - [c12]Ronald G. Dreslinski, Korey Sewell, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge:
Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems. Hot Chips Symposium 2012: 1-44 - [c11]Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke:
Composite Cores: Pushing Heterogeneity Into a Core. MICRO 2012: 317-328 - 2011
- [j2]Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das:
RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distributed Comput. 71(5): 625-640 (2011) - [j1]Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das:
Aérgia: A Network-on-Chip Exploiting Packet Latency Slack. IEEE Micro 31(1): 29-41 (2011) - 2010
- [c10]Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li:
Cost-driven 3D integration with interconnect layers. DAC 2010: 150-155 - [c9]Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das:
Aérgia: exploiting packet latency slack in on-chip networks. ISCA 2010: 106-116
2000 – 2009
- 2009
- [c8]Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das:
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA 2009: 175-186 - [c7]Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das:
Application-aware prioritization mechanisms for on-chip networks. MICRO 2009: 280-291 - [c6]Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das:
A case for dynamic frequency tuning in on-chip networks. MICRO 2009: 292-303 - [c5]Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir:
A case for integrated processor-cache partitioning in chip multiprocessors. SC 2009 - 2008
- [c4]Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das:
Performance and power optimization through data compression in Network-on-Chip architectures. HPCA 2008: 215-225 - [c3]Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das:
MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA 2008: 251-261 - 2007
- [c2]Dongkook Park, Reetuparna Das, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Ravishankar R. Iyer, Chita R. Das:
Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. Hot Interconnects 2007: 15-20 - [c1]Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das:
A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA 2007: 138-149
Coauthor Index
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