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ORCIDRui Liu 0005
Person information
- affiliation: Arizona State University, School of Electrical, Computer, and Energy Engineering, Tempe, AZ, USA
Other persons with the same name
- Rui Liu — disambiguation page
- Rui Liu 0001 — University of Delaware, Department of Computer and Information Sciences, Newark, DE, USA
- Rui Liu 0002
![[0000-0001-9061-787X]](https://dblp.org/img/orcid-mark.12x12.png "0000-0001-9061-787X")
— University of Chicago, Department of Computer Science, IL, USA (and 3 more) - Rui Liu 0003 — Colorado School of Mines, Department of Mechanical Engineering, Golden, CO, USA
- Rui Liu 0004 — National University of Singapore (and 1 more)
- Rui Liu 0006 — Louisiana Tech University, Ruston, LA, USA
- Rui Liu 0007 — Beihang University, School of Computer Science and Engineering, State Key Lab of Software Development Environment, Beijing, China
- Rui Liu 0008 — Inner Mongolia University, College of Computer Science, Hohhot, China
- Rui Liu 0009 — South China University of Technology, School of Mathematics, Guangzhou, China (and 2 more)
- Rui Liu 0010 — Technical University Munich, Germany
- Rui Liu 0011 — University of Saskatchewan, Department of Electrical and Computer Engineering, Saskatoon, Canada
- Rui Liu 0012 — The Second Xiangya Hospital of Central South University, Department of Oncology, Hunan, China
- Rui Liu 0013 — University of Michigan, Ann Arbor, MI, USA
- Rui Liu 0014 — Dartmouth College, Hanover, NH, USA (and 2 more)
- Rui Liu 0015 — Dalian University, School of Software Engineering, China
- Rui Liu 0016 — Zhejiang University, College of Information Science and Electronic Engineering, Hangzhou, China
- Rui Liu 0017 — University of California San Diego, Department of Physics, CA, USA (and 1 more)
- Rui Liu 0018 — Chang'an University, School of Automobile, Xi'an, China (and 1 more)
- Rui Liu 0019 — Chinese University of Hong Kong, Department of Electrical Engineering, CUHK-SenseTime Joint Laboratory, Hong Kong (and 1 more)
- Rui Liu 0020 — Beihang University, Sino-German Joint Software Institute, Beijing, China
- Rui Liu 0021 — North China Electric Power University, Beijing, China
- Rui Liu 0022 — Harbin Institute of Technology, Shenzhen Graduate School, China (and 1 more)
- Rui Liu 0023 — Ningxia University, School of Agriculture, Yinchuan, China
- Rui Liu 0024 — North University of China, MOE Key Laboratory of Instrumentation Science and Dynamic Measurement, Taiyuan, China
- Rui Liu 0025 — Beihang University, School of Mechanical Engineering and Automation, Beijing, China
- Rui Liu 0026 — Nanjing Tech University, School of Mechanical and Power Engineering, China (and 1 more)
- Rui Liu 0027 — Space Engineering University, School of Space Information, Beijing, China
- Rui Liu 0028 — University of Science and Technology Beijing, School of Automation and Electrical Engineering / Institute of Artificial Intelligence, China
- Rui Liu 0029 — Chengdu University of Technology, College of Geophysics, MOE Key Laboratory of Earth Exploration and Information Technology, China
- Rui Liu 0030 — Boston University, Division of Systems Engineering, Quincy, MA, USA (and 1 more)
- Rui Liu 0031 — Indiana University, Department of Computer and Information Science, IN, USA (and 1 more)
- Rui Liu 0032 — Chinese Academy of Sciences, Institute of Information Engineering, China (and 1 more)
- Rui Liu 0033 — City University of Hong Kong, Department of Mechanical Engineering, Hong Kong
- Rui Liu 0034 — Nanyang Technological University, Singapore
- Rui Liu 0035 — Chongqing University, College of Computer Science, Chongqing, China
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2020 – today
- 2020
[j6]Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun:
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(1): 189-202 (2020)- [j5]Xiaochen Peng, Rui Liu, Shimeng Yu:
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1333-1343 (2020) - [c15]Hongwu Jiang, Rui Liu, Shimeng Yu:
8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator. MWSCAS 2020: 257-260
2010 – 2019
- 2019
- [j4]Manqing Mao, Xiaochen Peng, Rui Liu, Jingtao Li, Shimeng Yu, Chaitali Chakrabarti:
MAX2: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 398-410 (2019) - [j3]Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang:
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4172-4185 (2019) - [c14]Zhilu Ye, Rui Liu, Hugh J. Barnaby, Shimeng Yu:
Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for Inference. IRPS 2019: 1-4 - [c13]Xiaochen Peng, Rui Liu, Shimeng Yu:
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture. ISCAS 2019: 1-5 - [c12]Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang:
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. ISSCC 2019: 396-398 - [i1]Fuxi Cai, Suhas Kumar, Thomas Van Vaerenbergh, Rui Liu, Can Li, Shimeng Yu, Qiangfei Xia, J. Joshua Yang, Raymond G. Beausoleil, Wei Lu, John Paul Strachan:
Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization. CoRR abs/1903.11194 (2019) - 2018
- [j2]Rui Liu, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu:
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3459-3468 (2018) - [c11]Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu:
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. ASP-DAC 2018: 574-579 - [c10]Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu:
Parallelizing SRAM arrays with customized bit-cell for binary neural networks. DAC 2018: 21:1-21:6 - [c9]Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu:
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. DATE 2018: 1423-1428 - [c8]Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang:
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC 2018: 496-498 - 2017
- [j1]Xiaoyu Sun, Rui Liu, Yi-Ju Chen, Hsiao-Yun Chiu, Wei-Hao Chen, Meng-Fan Chang, Shimeng Yu:
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2962-2965 (2017) - [c7]Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu:
Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module. AsianHOST 2017: 67-72 - [c6]Rui Liu, Heng-Yuan Lee, Shimeng Yu:
Analyzing inference robustness of RRAM synaptic array in low-precision neural network. ESSDERC 2017: 18-21 - [c5]Rui Liu, Pai-Yu Chen, Shimeng Yu:
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array. ISCAS 2017: 1-4 - 2016
- [c4]Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia:
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM. ACM Great Lakes Symposium on VLSI 2016: 299-304 - [c3]Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu:
A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation. HOST 2016: 13-18 - 2015
- [c2]Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu:
Exploiting resistive cross-point array for compact design of physical unclonable function. HOST 2015: 26-31 - [c1]Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu:
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. ISCAS 2015: 193-196
Coauthor Index
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