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ORCIDWei Shi 0011
Person information
- affiliation (PhD 2022): University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, TX, USA
- affiliation (until 2017): Zhejiang University, Hangzhou, China
Other persons with the same name
- Wei Shi — disambiguation page
- Wei Shi 0001
![[0000-0002-3071-8350]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-3071-8350")
— Carleton University, School of Infermation Technology, Faculty of Engineering and Design, Ottawa, ON, Canada (and 3 more) - Wei Shi 0002 — National Oceanic and Atmospheric Administration, College Park, MD, USA (and 1 more)
- Wei Shi 0003 — Chinese University of Hong Kong, Hong Kong
- Wei Shi 0004 — Central South University, School of Aeronautics and Astronautics, Changsha, China
- Wei Shi 0005 — Bundeswehr University Munich, Germany
- Wei Shi 0006 — Qingdao University of Science and Technology, School of Information Science and Technology, China (and 1 more)
- Wei Shi 0007 — Université Laval, Centre for Optics, Photonics and Lasers, Québec, Canada (and 1 more)
- Wei Shi 0008 — Kyushu University, ICER, Innovation Center for Educational Resources, Japan
- Wei Shi 0009 — Peking University, Shenzhen Graduate School, Key Laboratory of Machine Perception, Beijing, China
- Wei Shi 0010 — Arizona State University, School of Electrical, Computer and Energy Engineering, Phoenix, AZ, USA (and 4 more)
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2020 – today
- 2025
[j7]Linran Zhao, Yan Gong, Xiang Liu, Wei Shi, Yiming Han, Wen Li, Yaoyao Jia:
NeuroFlare: An mm3-Scale Wireless Neural Interface Device With Simultaneous Neural Recording and Optical Stimulation. IEEE J. Solid State Circuits 60(9): 3342-3354 (2025)- [j6]Linran Zhao, Yan Gong, Raymond G. Stephany, Wei Shi, Wen Li, Yaoyao Jia:
An Energy-Efficient and Artifact-Resilient ASIC for Simultaneous Neural Recording and Optogenetic Stimulation. IEEE Trans. Biomed. Circuits Syst. 19(4): 791-802 (2025) - [c15]Tao Liu, Qi Xu, Wei Shi, Zhigang Hua, Shuang Yang:
Session-Level Dynamic Ad Load Optimization using Offline Robust Reinforcement Learning. KDD (1) 2025: 2458-2468 - 2024
- [c14]Wei Shi, Chen Fu, Qi Xu, Sanjian Chen, Jizhe Zhang, Qinqin Zhu, Zhigang Hua, Shuang Yang:
Ads Supply Personalization via Doubly Robust Learning. CIKM 2024: 4874-4881 - [c13]Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang:
PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. DAC 2024: 47:1-47:6 - [c12]Linran Zhao, Wei Shi, Yan Gong, Xiang Liu, Wen Li, Yaoyao Jia:
33.9 A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend. ISSCC 2024: 558-560 - 2023
- [j5]Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun:
A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. IEEE J. Solid State Circuits 58(9): 2564-2574 (2023) - [c11]Linran Zhao, Yan Gong, Wei Shi, Raymond Stephany, Wen Li, Yaoyao Jia:
A Wireless Implantable Opto-Electro Neural Interface ASIC for Simultaneous Neural Recording and Stimulation. CICC 2023: 1-2 - 2022
- [j4]Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun, Bo Liu:
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1209-1221 (2022) - [c10]Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan:
Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. ASP-DAC 2022: 519-525 - [c9]Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun:
A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM. CICC 2022: 1-2 - [c8]Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun:
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. MLCAD 2022: 35-41 - [i1]Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun:
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. CoRR abs/2207.06412 (2022) - 2021
- [c7]Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun:
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. ISSCC 2021: 170-172 - [c6]Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun:
A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. ISSCC 2021: 376-378 - [c5]Linxiao Shen, Zijie Gao, Xiangxing Yang, Wei Shi, Nan Sun:
A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR. ISSCC 2021: 382-384 - 2020
- [j3]Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun:
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits 55(4): 1011-1022 (2020) - [j2]Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun:
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits 55(12): 3248-3259 (2020) - [c4]Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan:
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC 2020: 1-6 - [c3]Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun:
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC 2020: 162-164
2010 – 2019
- 2019
- [j1]Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu:
A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits 54(12): 3375-3385 (2019) - [c2]Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun:
A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor. ISSCC 2019: 64-66 - [c1]Xiyuan Tang, Begum Kasap, Linxiao Shen, Xiangxing Yang, Wei Shi, Nan Sun:
An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. VLSI Circuits 2019: 140-
Coauthor Index
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last updated on 2025-09-27 20:09 CEST by the dblp team
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