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Masayoshi Tachibana
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2010 – 2019
- 2018
- [j7]Nattagit Jiteurtragool, Masayoshi Tachibana, Wimol San-Um:
Robustification of a One-Dimensional Generic Sigmoidal Chaotic Map with Application of True Random Bit Generation. Entropy 20(2): 136 (2018) - [j6]Chatchai Wannaboon, Nattagit Jiteurtragool, Wimol San-Um, Masayoshi Tachibana:
Phase difference analysis technique for parametric faults BIST in CMOS analog circuits. IEICE Electron. Express 15(9): 20180175 (2018) - 2017
- [j5]Patinya Ketthong, Wimol San-Um, Banlue Srisuchinwong, Masayoshi Tachibana:
A simple current-reversible chaotic jerk circuit using inherent tanh(x) of an opamp. IEICE Electron. Express 14(17): 20170192 (2017) - 2015
- [c6]Nattagit Jiteurtragool, Chatchai Wannaboon, Masayoshi Tachibana:
True Random Number Generator based on compact chaotic oscillator. ISCIT 2015: 315-318 - [c5]Chatchai Wannaboon, Masayoshi Tachibana:
An autonomous chaotic oscillator based on hyperbolic tangent nonlinearity. ISCIT 2015: 323-326 - 2013
- [j4]Jun Yuan, Masayoshi Tachibana:
A resistance matching based self-testable current-mode R-2R digital-to-analog converter. IEICE Electron. Express 10(23): 20130753 (2013) - 2012
- [j3]Jun Yuan, Masayoshi Tachibana:
A common-mode BIST technique for fully-differential sample-and-hold circuits. IEICE Electron. Express 9(13): 1128-1134 (2012) - 2011
- [c4]Jun Yuan, Masayoshi Tachibana:
A BIST scheme for operational amplifier by checking the stable output of transient response. ECCTD 2011: 885-888 - 2010
- [j2]Wimol San-Um, Masayoshi Tachibana:
A Fault Signature Characterization Based Analog Circuit Testing Scheme and the Extension of IEEE 1149.4 Standard. IEICE Trans. Inf. Syst. 93-D(1): 33-42 (2010) - [c3]Wimol San-Um, Masayoshi Tachibana:
A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration. ISCAS 2010: 1931-1934
2000 – 2009
- 2009
- [c2]Wimol San-Um, Masayoshi Tachibana:
Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits. SBCCI 2009
1980 – 1989
- 1989
- [c1]Masayoshi Tachibana, Yoshihisa Kondo, Yasuo Yamada, Masafumi Takahashi, Haruyuki Tago:
High performance I/O processors for real-time pulse handling. ICCD 1989: 415-418 - 1986
- [j1]Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki:
A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4): 466-476 (1986)
Coauthor Index
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