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ORCIDRajeev R. Rao
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2010 – 2019
- 2013
[j7]Victor V. Zyuban, Scott A. Taylor, Birger Christensen, A. R. Hall, Christopher J. Gonzalez, Joshua Friedrich, Frances Clougherty, Jon Tetzloff, Rajeev R. Rao:
IBM POWER7+ design for higher frequency at fixed power. IBM J. Res. Dev. 57(6) (2013)
2000 – 2009
- 2009
- [j6]Rajeev R. Rao, Vivek Joshi, David T. Blaauw, Dennis Sylvester:
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic. ACM Trans. Design Autom. Electr. Syst. 15(1): 5:1-5:27 (2009) - 2007
- [j5]Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester:
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 468-479 (2007) - 2006
- [j4]Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester:
Analytical yield prediction considering leakage/performance correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1685-1695 (2006) - [c8]Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester:
An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169 - [c7]Rajeev R. Rao, David T. Blaauw, Dennis Sylvester:
Soft error reduction in combinational logic using gate resizing and flipflop selection. ICCAD 2006: 502-509 - [c6]Vivek Joshi, Rajeev R. Rao, David T. Blaauw, Dennis Sylvester:
Logic SER Reduction through Flipflop Redesign. ISQED 2006: 611-616 - 2005
- [j3]Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Anirudh Devgan:
Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Des. Test Comput. 22(4): 376-385 (2005) - [j2]Rajeev R. Rao, Harmander Deogun, David T. Blaauw, Dennis Sylvester:
Bus encoding for total power reduction using a leakage-aware buffer configuration. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1376-1383 (2005) - [c5]Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif:
An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93 - 2004
- [j1]Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester:
Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 131-139 (2004) - [c4]Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester:
Parametric yield estimation considering leakage variability. DAC 2004: 442-447 - [c3]Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David T. Blaauw:
Leakage-and crosstalk-aware bus encoding for total power reduction. DAC 2004: 779-782 - 2003
- [c2]Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester:
Statistical estimation of leakage current considering inter- and intra-die process variation. ISLPED 2003: 84-89 - [c1]Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge:
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18
Coauthor Index
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