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ORCIDLiang Qi 0002
Person information
- affiliation: Shanghai Jiao Tong University, Shanghai, China
- affiliation (PhD): University of Macau, Macau, China
Other persons with the same name
- Liang Qi — disambiguation page
- Liang Qi 0001
![[0000-0002-0762-5607]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-0762-5607")
— Shandong University of Science and Technology, Qingdao, China (and 1 more) - Liang Qi 0003 — Jiangsu University of Science and Technology, Zhenjiang, China
- Liang Qi 0004 — Center for Physical Sciences and Technology, Vilnius, Lithuania
- Liang Qi 0005 — Nanjing Forestry University, Nanjing, China
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2020 – today
- 2025
[j23]Ke Li, Haoyu Gong, Xianyu Congzhou, Zhensheng Li, Liang Qi, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin:
A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering. IEEE J. Solid State Circuits 60(3): 838-849 (2025)- [j22]Jieyu Li, Weifeng He, Bo Zhang, Chuxiong Lin, Liang Qi, Dingxuan Liu, Mingoo Seok:
A 394-TOPS/W Matched Filter With Charge-Domain Computing for GPS Signal Acquisition. IEEE J. Solid State Circuits 60(5): 1805-1817 (2025) - 2024
- [j21]Zhouchen Ma, Cheng Chen, Yuxiang Lin, Liang Qi, Yongfu Li, Xia Bi, Mohamad Sawan, Guoxing Wang, Jian Zhao:
An Energy-Efficient FD-fNIRS Readout Circuit Employing a Mixer-First Analog Frontend and a $\Sigma$-$\Delta$ Phase-to-Digital Converter. IEEE Trans. Biomed. Circuits Syst. 18(4): 938-950 (2024) - [c32]Ke Li, Xianyu Congzhou, Liang Qi, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin:
A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering. CICC 2024: 1-2 - [c31]Xinyu Qin, Yichen Jin, Guoxing Wang, Sai-Weng Sin, Maurits Ortmanns, Yong Lian, Liang Qi:
A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS. CICC 2024: 1-2 - [c30]Ran Zhang, Ka-Fai Un, Zhensheng Li, Mingqiang Guo, Liang Qi, Rui Paulo Martins, Sai-Weng Sin:
Invited Paper: A Ping-Pong Analog Delta Generator for Delt-Sigma Computing-In-Memory SRAM Macro for Edge AI Processing. ICTA 2024: 84-87 - [c29]Meng Guo, Yuekai Liu, Jinlei Pan, Liang Qi:
Comparative Study for Different Loop-Filter Architectures of 2x Time-Interleaved CT DSM. ISCAS 2024: 1-5 - [c28]Ran Zhang, Ka-Fai Un, Mingqiang Guo, Liang Qi, Dengke Xu, Weibing Zhao, Rui Paulo Martins, Franco Maloberti, Sai-Weng Sin:
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation. ISCAS 2024: 1-5 - 2023
- [j20]Shulin Zhao, Mingqiang Guo, Liang Qi, Dengke Xu, Guoxing Wang, Rui Paulo Martins, Sai-Weng Sin:
A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward. IEEE J. Solid State Circuits 58(10): 2722-2732 (2023) - [j19]Tao He, Jing Luo, Zhen Kong, Xu Liang, Longyang Lin, Bo Zhao, Liang Qi, Yongfu Li, Guoxing Wang, Jian Zhao:
A Re-Configurable Body Channel Transceiver Towards Wearable and Flexible Biomedical Sensor Networks. IEEE Trans. Biomed. Circuits Syst. 17(5): 1022-1034 (2023) - [j18]Huaiyu Liu, Yang Lin, Liang Qi, Yongwei Lou, Guoxing Wang, Yan Liu:
Analysis and Design of VCO-Based Neural Front-End With Mixed Domain Level-Crossing for Fast Artifact Recovery. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 1214-1227 (2023) - [j17]Yue Hu, Yuekai Liu, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi:
A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4729-4741 (2023) - [j16]Mingqiang Guo, Liang Qi, Weibing Zhao, Gang Xiao, Rui Paulo Martins, Sai-Weng Sin:
A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4767-4780 (2023) - [j15]Gaofeng Tan, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi:
A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4781-4792 (2023) - [j14]Jingying Zhang, Sai-Weng Sin, Yan Liu, Fan Ye, Guoxing Wang, Maurits Ortmanns, Liang Qi:
On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 356-360 (2023) - [j13]Kaiquan Chen, Biao Wang, Yan Liu, Fan Ye, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi:
A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2724-2728 (2023) - [c27]Yuekai Liu, Jinlei Pan, Liang Qi:
A CT DSM with DAC Scaling Technique for Direct Neural Recording Front-End. ASICON 2023: 1-4 - [c26]Ruiqi Gao, Mingqiang Guo, Sai-Weng Sin, Liang Qi, Biao Wang, Guoxing Wang, Rui Paulo Martins:
Weightings in Incremental ADCs: A Tutorial Review. CICC 2023: 1-8 - [c25]Yuhan Pan, Qingxun Wang, Kaiquan Chen, Bin Cai, Jiuchao Qian, Yong Lian, Liang Qi:
A Two-step Linear-Exponential Incremental ADC with Slope Extended Counting. ISCAS 2023: 1-5 - [c24]Qingxun Wang, Yuhan Pan, Kaiquan Chen, Yu Lin, Biao Wang, Liang Qi:
A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling. ISCAS 2023: 1-5 - [c23]Jieyu Li, Weifeng He, Bo Zhang, Liang Qi, Guanghui He, Mingoo Seok:
CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition. ISSCC 2023: 430-431 - [c22]Qingxun Wang, Kaiquan Chen, Liang Qi:
A Zoom Architecture Using Linear-Exponential Incremental ADC. NEWCAS 2023: 1-5 - 2022
- [j12]Kaiquan Chen, Mingyi Chen, Longlong Cheng, Liang Qi, Guoxing Wang, Yong Lian:
A 124 dB dynamic range sigma-delta modulator applied to non-invasive EEG acquisition using chopper-modulated input-scaling-down technique. Sci. China Inf. Sci. 65(4) (2022) - [j11]Mingqiang Guo, Sai-Weng Sin, Liang Qi, Dengke Xu, Guoxing Wang, Rui Paulo Martins:
Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2564-2569 (2022) - [j10]Liang Qi, Yuekai Liu, Sai-Weng Sin, Xinpeng Xing, Guoxing Wang, Maurits Ortmanns, Rui Paulo Martins:
Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2623-2628 (2022) - [j9]Huaiyu Liu, Tongtong Guo, Peng Yan, Liang Qi, Mingyi Chen, Guoxing Wang, Yan Liu:
A Hybrid 1st/2nd-Order VCO-Based CTDSM With Rail-to-Rail Artifact Tolerance for Bidirectional Neural Interface. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2682-2686 (2022) - [j8]Huaiyu Liu, Liang Qi, Guoxing Wang, Yan Liu:
A VCO-Based CTDSM With Integrated Phase Error Correction for Neural Interface. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4018-4022 (2022) - [j7]Jiajie Huang, Ting Zhou, Huaiyu Liu, Liang Qi, Yan Liu, Yongfu Li:
Low-Noise, High-Linearity Sine-Wave Generation Using Noise-Shaping Phase-Switching Technique. IEEE Trans. Instrum. Meas. 71: 1-7 (2022) - [c21]Mingqiang Guo, Sai-Weng Sin, Liang Qi, Gang Xiao, Rui Paulo Martins:
A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing. CICC 2022: 1-2 - [c20]Cheng Chen, Zhouchen Ma, Yaxin Liu, Zhenhong Liu, Linfeng Zhou, Yan Wu, Liang Qi, Yongfu Li, Mohamad Sawan, Guoxing Wang, Jian Zhao:
A Sub-0.01° Phase Resolution 6.8-mW fNIRS Readout Circuit Employing a Mixer-First Frequency-Domain Architecture. ESSCIRC 2022: 229-232 - [c19]Ke Li, Sai-Weng Sin, Liang Qi, Weibing Zhao, Guoxing Wang, Rui Paulo Martins:
A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC. ISCAS 2022: 551-555 - 2021
- [j6]Chao Wang, Yuxin Ji, Ce Ma, Qiao Cai, Liang Qi, Yongfu Li:
An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique. IEEE Access 9: 79904-79910 (2021) - [j5]Dongyang Jiang, Liang Qi, Sai-Weng Sin, Franco Maloberti, Rui Paulo Martins:
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation. IEEE J. Solid State Circuits 56(8): 2375-2387 (2021) - [j4]Ahmed Reda Mohamed, Liang Qi, Guoxing Wang:
A power-efficient and re-configurable analog artificial neural network classifier. Microelectron. J. 111: 105022 (2021) - [c18]Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang:
Advances in Continuous-time MASH ΔΣ Modulators. ASICON 2021: 1-4 - [c17]Hongyi Liu, Xiangao Qi, Yuqing Lou, Liang Qi, Zuo-Wei Yeh, Kea-Tiong Tang, Jian Zhao:
Low-Hardware-Cost SNN employing FeFET-based Neurons with Tunable Leaky Effect. BioCAS 2021: 1-4 - [c16]Zhuo Gao, Mingyi Chen, Liang Qi, Yongfu Li, Jun Yan:
An Adaptively-controlled High-efficiency Buck Converter with Wide Dynamic Range for IoT Applications. ICTA 2021: 145-146 - [c15]Yue Hu, Jingying Zhang, Yang Zhao, Mingyi Chen, Liang Qi:
Discrete-Time MASH Delta-Sigma Modulator with an IIR-based Self-Coupling. ICTA 2021: 181-182 - [c14]Tao He, Zhen Kong, Xu Liang, Jing Luo, Longyang Lin, Liang Qi, Yongfu Li, Jian Zhao, Guoxing Wang:
A 10-Mbps 119.2-pJ/bit Software Defined Body Channel Transceiver Employing a CCII-based PGA and a 2.5-bit/cycle ADC in 180-nm CMOS. ICTA 2021: 206-207 - [c13]Jiliang Zhang, Gaofeng Tan, Yue Hu, Jian Zhao, Mingyi Chen, Yongfu Li, Liang Qi:
A Multi-Rate Hybrid DT/CT Mash ΔΣ Modulator with High Tolerance to Noise Leakage. ISCAS 2021: 1-5 - [c12]Weifu Chen, Mingyi Chen, Yuzhi Hao, Liang Qi, Jian Zhao:
A 1-μA-Quiescent-Current Capacitor-Less LDO Regulator with Adaptive Embedded Slew-Rate Enhancement Circuit. ISCAS 2021: 1-5 - [c11]Ce Ma, Yuxin Ji, Cai Qiao, Ting Zhou, Liang Qi, Yongfu Li:
An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0V. ISCAS 2021: 1-5 - [c10]Xinyu Qin, Jingying Zhang, Liang Qi, Sai-Weng Sin, Rui Paulo Martins, Guoxing Wang:
Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications. ISCAS 2021: 1-5 - [c9]Jingying Zhang, Yang Zhao, Mingyi Chen, Chixiao Chen, Fan Ye, Liang Qi:
Self-coupled MASH Delta-Sigma Modulator with Zero Optimization. ISOCC 2021: 1-2 - [c8]Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren:
Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. ISOCC 2021: 246-247 - [c7]Liang Qi, Tianming Ni, Xinyu Qin, Mingyi Chen, Yongfu Li, Guoxing Wang:
Continuous-time Delta-Sigma Modulators: Single-loop versus MASH. ISOCC 2021: 252-253 - [c6]Mingyi Chen, Yuzhi Hao, Liang Qi, Yongfu Li, Jun Yan:
Implement Tunable Sub-TΩ On-chip Resistor for Vital Signal Acquisition: A Review. ISOCC 2021: 280-281 - 2020
- [j3]Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, Rui Paulo Martins, Maurits Ortmanns:
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. IEEE J. Solid State Circuits 55(2): 344-355 (2020) - [j2]Ahmed Reda Mohamed, Liang Qi, Yongfu Li, Guoxing Wang:
A Generic Nano-Watt Power Fully Tunable 1-D Gaussian Kernel Circuit for Artificial Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1529-1533 (2020) - [c5]Gaofeng Tan, Haolin Lu, Xinyu Qin, Jiliang Zhang, Jingying Zhang, Yan Liu, Liang Qi:
A Self-coupled DT MASH ΔΣ Modulator with High Tolerance to Noise Leakage. APCCAS 2020: 90-93 - [c4]Dongyang Jiang, Liang Qi, Sai-Weng Sin, Franco Maloberti, Rui Paulo Martins:
A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c3]Liang Qi, Sai-Weng Sin, Rui Paulo Martins:
Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications. ASICON 2019: 1-4 - [c2]Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, Rui Paulo Martins, Maurits Ortmanns:
A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS. ISSCC 2019: 336-338 - 2018
- [c1]Yanquan Luo, Liang Qi, Ankesh Jain, Maurits Ortmanns:
A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch. ISCAS 2018: 1-5 - 2017
- [j1]Liang Qi, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(10): 2641-2654 (2017)
Coauthor Index
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