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ORCID13th ASICON 2019: Chongqing, China
- 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019. IEEE 2019, ISBN 978-1-7281-0735-6
- Wei Liu, Weilin Cong, Chengyu Hu, Peng Lu, Jinmei Lai:
Balance of memory footprint and runtime for high-density routing in large-scale FPGAs. 1-4 - Cong Lai, Guangyu Wang, Qingyu Yang, Hongbin Sun:
Efficient Photometric Alignment for Around View Monitor System. 1-4 - Xiaoxu Kang, Xiaolan Zhong, Ming Li:
Development and Optimization of Contact Module Process for Micro-Bridge Structure based MEMS/Sensor Application. 1-4 - Weijing Wen, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng:
Learning Sparse Patterns in Deep Neural Networks. 1-4 - Yuting Yao, Jipeng Wei, Manxin Li, Shunli Ma, Fan Ye, Junyan Ren:
A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. 1-4 - Lei Liu, Yao Yao
, Meng-Qi Wen, Yue Li, David Wei Zhang:
A pn-Coupled Superjunction IGBT for High Switching Speed. 1-4 - Lin Li, Qiu Huang, Jianhao Hu, Jienan Chen:
A Novel Signed Bit-serial Fixed-point Accumulator with Configurable Overflow-Protection Precision. 1-4 - Jinguo Huang, Yingcheng Lin, Wei He, Xichuan Zhou, Cong Shi, Nanjian Wu, Gang Luo:
High-speed Classification of AER Data Based on a Low-cost Hardware System. 1-4 - Kazuhiko Endo:
Post-Si Nano Device Technology. 1 - Qiuhong Ying, Lun-Yao Wang, Zhufei Chu, Yinshui Xia:
Area Optimization of MPRM Circuits Using Approximate Computing. 1-4 - Ming Zhang, Nicolas Llaser:
High Intensity Focused Ultrasound for Noninvasive Medical Applications. 1-4 - Yue Zhao, Tong Li, Feng Dong, Qin Wang, Weifeng He, Jianfei Jiang:
A New Approximate Multiplier Design for Digital Signal Processing. 1-4 - Takuya Asuke, Ryo Kishida, Jun Furuta, Kazutoshi Kobayashi:
Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation. 1-4 - Jun Qiao, Xiao Wang, Yaohong Zhao:
Design of High Dynamic Range and Digitalized Readout Integrated Circuit for LWIR FPAs. 1-3 - Yu-Cheng Su, Kang-Yu Chang, Yu-Tung Chin, Chia-Wen Chang, Shyh-Jye Jou:
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays. 1-4 - Yangyang Chang, Gerald E. Sobelman, Xiaofang Zhou:
Genetic Architecture Search for Binarized Neural Networks. 1-4 - Xiao Shi, Jinlong Yan, Hao Yan, Jiajia Zhang, Jinxin Wang, Longxing Shi, Lei He:
Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap Resampling. 1-4 - Huashu Wang, Wei Ma, Zhiming Xiao, Wei-Chih Cheng, Liang Wang, Fanming Zeng, Hongyu Yu, Weibo Hu:
The Design and Performance Comparison of Wide Bandwidth LNA with Three Different Kinds of Technologies. 1-4 - Huaidong Gao, Fan Yang, Dian Zhou, Xuan Zeng:
Parallel Global Placement on CPU via Parallel Reduction. 1-4 - Abdulraqeb Abdullah Saeed Abdo, Jie Ling, Pinghua Chen:
Architecture considerations of LTE/WCDMA wideband power amplifier for efficiency improvement. 1-4 - Xiaozhi Kang, Xiaoxu Kang, Zijian Zhao, Jingxiu Ding, Yi Hu, Dapeng Xu, Qingqing Sun, David Wei Zhang:
Low-Dropout Regulator design with a simple structure for good high frequency PSRR performance based on Bandgap Circuit. 1-4 - Min Zhang, Peng Huang, Yizhou Zhang, Yachen Xiang, Runze Han, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang:
FNSim: A Device-Circuit-Algorithm Codesigned Simulator for Flash based Neural Network. 1-4 - Xian Zhang, Yong Xu:
High precision low power CMOS bandgap for RFID. 1-4 - Muchan Li, Pei Peng, Zhongzheng Tian, Liming Ren, Yunyi Fu:
Adsorbates on Multilayer Graphene Surface: Morphology, Distribution and Electrical Properties. 1-4 - Yulong Zhu, Futian Liang, Xinzhe Wang, Bo Feng, Chenxi Zhu, Ge Jin:
An ASIC for Discriminating Single Photon Detector Signal of High-Speed Quantum Key Distribution System. 1-4 - Yan-Ming Li, Xiao-Xiao Wang, Xiao-Li Xi, Jian Sun, Zhong-Hui Chen:
A FT Trimming Circuit Based on EPROM and Pin Multiplexing. 1-4 - Riho Aoki, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Yuto Sasaki, Kosuke Machida, Takayuki Nakatani, Jianlong Wang, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Evaluation of Null Method for Operational Amplifier Short-Time Testing. 1-4 - Xiaotian Zhang, Pengjun Wang, Yunfei Yu, Yuejun Zhang, Shunxin Ye:
A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback. 1-4 - Ran Cheng, Ming Tian, Changfeng Wang, Zhimei Cai, Jie Zhang, Yan-Yan Zhang, Yi Zhao:
Performance Investigation of Uniaxially Tensile Stressed Ge n-FinFETs Formed on Biaxially Strained GeOI Substrates And Its Impact On Ge CMOS Inverters. 1-4 - Lintao Li, Jiangyi Shi, Zhixiong Di:
High Parallel VLSI Architecture Design of BPC in JPEG2000. 1-4 - Junning Jiang, Liang Cai, Feng Dong, Kehua Yu, Ke Chen, Wei Qu, Jianfei Jiang:
Deploying and Optimizing Convolutional Neural Networks on Heterogeneous Architecture. 1-4 - Yue Shi, Jiawen Wang, Jianwen Cao, Zekun Zhou:
An Ultra-Low Power Cycle-by-Cycle Current Limiter Suitable for Switching-Mode Power Supply with 2.2 MHz Frequency. 1-4 - Fuqiang Liu, Mingfeng Chen, Heng Ma, Zhiliang Hong:
Dual-Loop-Controlled AC-Coupling 100MHz Bandwidth Envelope Tracking Modulator for 5G RF Power Amplifier. 1-4 - Hao Li, Hongmei Yu, Dongsheng Liu, Peng Liu, Bo Liu:
A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module. 1-4 - Lili Zhang, Wen Kuang:
Research and Implementation of TPC Coding In High Bit Rate Telemetry System. 1-4 - Mingfeng Chen, Fuqiang Liu, Heng Ma, Zhiliang Hong:
High-Bandwidth Wide-Output-Swing Linear Amplifier for LTE-100MHz Envelope Tracking. 1-4 - Jiafeng Liu, Zhiyin Lu, Xie Xie, Jian Wang, Jinmei Lai:
An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform. 1-4 - Jiachen Jiang, Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun:
Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections. 1-4 - Yu Ma, Linfeng Zheng, Pingqiang Zhou:
CoDRAM: A Novel Near Memory Computing Framework with Computational DRAM. 1-4 - Yi Zhang, Xiaoshan He, Ming-e Jing, Yibo Fan, Xiaoyang Zeng:
Enhanced Recursive Residual Network for Single Image Super-Resolution. 1-4 - Junwei Yang, Weiwei Shi, Zhiyu Huang, Yuan Xu, Yanghao Zheng, Xuanbin Fang:
A Optimized PPD CMOS Pixel with 26.09 % Transfer Efficiency Improvement and 43.34 % Crosstalk Suppression for I-ToF Application. 1-4 - Toufik Sadi, Oves Badami, Vihar P. Georgiev, Jie Ding, Asen Asenov:
Advanced Simulation of RRAM Memory Cells. 1-4 - Ang Hu, Dongsheng Liu, Zirui Jin, Cong Zhang, Ke-feng Zhang, Lan-qi Liu:
RF Transceiver System Design: From Protocols to Specifications. 1-4 - Chenxi Zhu, Futian Liang, Bo Feng, Xinzhe Wang, Yulong Zhu, Chengzhi Peng:
An adjustable amplitude and pulse-width laser modulation driver with active feedback for QKD experiments. 1-4 - Pengfeng Zhang, Jianping Hu:
Dual-Threshold Independent-Gate TFET with Tri-side Tunneling. 1-4 - Danyang Yang, Zibin Dai, Wei Li, Tao Chen:
An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit. 1-4 - Yang Yang Peng, Ping Li, Yang Li:
Reconfigurable RF Power Amplifier in 5G/4G with RF-SOI CMOS. 1-4 - Haoyang Zhou, Wei Li, Tao Wang, Jiao Ye, Chuangguo Wang:
A Class-F3 VCO with 104% Ultra-Wide Band Tuning Range and -125dBc/Hz Phase Noise. 1-4 - Zhimei Cai, Zhiyong Han, Ming Tian, Changfeng Wang, Xiaoming Hu, Ran Cheng, Yi Zhao:
Variation Analysis of Interconnect Capacitance and Process Corner in Advanced CMOS Process with Double Patterning Technology. 1-4 - Yufei Sun, Yanzhao Ma, Kai Cui, Xiaoya Fan:
A Low-Power Comparator-Less Relaxation Oscillator. 1-4 - Ruiqiang Song, Jinjin Shao, Bin Liang, Yaqing Chi, Jianjun Chen:
A Single-Event Upset Evaluation Approach Using Ion-Induced Sensitive Area. 1-4 - Wentao Lv, Xiaokang Niu, Lianming Li:
A 60GHz Digitally-Controlled Differential Reflection-type Phase Shifter in 65-nm CMOS with Low Phase Error. 1-4 - Khoa Van Pham, Tien Van Nguyen, Kyeong-Sik Min:
Defect-Tolerant and Energy-Efficient Training of Multi-Valued and Binary Memristor Crossbars for Near-Sensor Cognitive Computing. 1-4 - Xing Zhou, Siau Ben Chiah, Binit Syamal, Kenneth Eng-Kian Lee:
Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits. 1-4 - Xinyuan Qu, Zhihong Huang, Ning Mao, Yu Xu, Gang Cai, Zhen Fang:
A Grain-Adaptive Computing Structure for FPGA CNN Acceleration. 1-4 - Zhongshan Zheng, Zhentao Li, Bo Li, Jiajun Luo, Zhengsheng Han:
Influences of the Source and Drain Resistance of the MOSFETs on the Single Event Upset Hardness of SRAM cells. 1-3 - Zirui Jin, Ang Hu, Zilong Liu, Dongsheng Liu:
A 35µW Receiver Front-End with 35% wireless energy harvesting efficiency for Wearable Medical Applications. 1-4 - Yiran Sun, Ju Zhou, Shiying Zhang, Xuexiang Wang:
Buffer Sizing for Near-Threshold Clock Tree using Improved Genetic Algorithm. 1-4 - Lun Zhang, Weikang Qian, Hai-Bao Chen:
Area-Efficient Parallel Stochastic Computing with Shared Weighted Binary Generator. 1-4 - Horng-Chih Lin, Yu-An Huang:
A Platform with Exquisite Film Profile Engineering in Oxide-Based Thin-Film Transistors for More-than-Moore Applications. 1-3 - Makoto Nagata:
On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks: Invited Paper. 1-4 - Chongzhou Fang, Zaichen Zhang, Xiaohu You, Chuan Zhang:
Automatic Hardware Design Tool Based on Reusing Transformation. 1-4 - Peng Sun, Yun Li, Yao Yao, Peng-Fei Wang:
Study for NOR Flash cell burn out failure improvement in the advanced node below 65nm. 1-4 - Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang:
Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes. 1-4 - Yu Ma, Dingcheng Jia, Huifan Zhang, Ruoyu Wang, Pingqiang Zhou:
A Compact Memory Structure based on 2T1R Against Single-Event Upset in RRAM Arrays. 1-4 - Tao Wang, Wei Li, Haoyang Zhou, Jiao Ye, Yuanyuan Xu:
An 8-12GHz Class-F3 VCO with Multi-LC Tank in 28nm CMOS. 1-4 - Junxian He, Xichuan Zhou, Yingcheng Lin, Chonglei Sun, Cong Shi, Nanjian Wu, Gang Luo:
20, 000-fps Visual Motion Magnification on Pixel-parallel Vision Chip. 1-4 - Xiangnan Song, Shiying Zhang, Ju Zhou, Xuexiang Wang:
A Variation Aware Register Clustering Methodology in Near-Threshold Region. 1-4 - Sheng Zhang, Song Jia, Hanzun Zhang, Rongshan Wei, Weixin Gai:
Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop. 1-4 - Weiiie Xu, Yudi Zhao, Peng Huang, Xiaoyan Liu, Jinfeng Kang:
3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model. 1-4 - Yuan Cheng, Ngai Wong, Xiong Liu, Leibin Ni, Hai-Bao Chen, Hao Yu:
A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks. 1-4 - Xuefeng Ye, Duoduo Zeng, Xiangliang Jin, Yang Wang:
A Low-Temperature-Coefficient and High-PSRR Bandgap Reference for Readout Circuit of SPAD. 1-4 - Ziyun He, Shaoquan Liao, Zixin Wang, Jianping Guo:
A Power-Area-Efficient Low-Dropout Regulator With Enhanced Buffer Impedance Attenuation. 1-4 - Cong Liu, MouFu Kong, Hanzhi Chen, Bo Yi, Bingke Zhang, Xingbi Chen:
Simulation Study on Novel High Voltage Transient Voltage Suppression Diodes. 1-4 - Ye Yuan, Song Ma, Yuhua Cheng:
Circuit Design Challenges of ADC for the Application in Multiple Physiological Parameters Detection System. 1-4 - Jinfeng Kang, Peng Huang, Runze Han, Yachen Xiang, Xiaole Cui, Xiaoyan Liu:
Flash-based Computing in-Memory Scheme for IOT. 1-4 - Wenjie Huang, Qihui Zhang, Jing Li, Zhong Zhang, Heng Deng, Ning Ning, Qi Yu:
A Calibration Technique for Two-Step Single-Slope Analog-to-Digital Converter. 1-4 - Haoran Gong, Yunhao Fu, Ning Ding, Jiaqi Jiang, Yuchun Chang:
A Readout Circuit of Microchannel Plate Light Detector in 0.13um CMOS Technology. 1-4 - Jiahao Lu, Xianghua Luo, Dongsheng Liu, Peng Liu, Bo Liu:
A Configurable Architecture of ANN in Hardware with Resource-Efficient Reusable Neuron. 1-4 - Hanze Zheng, Yinshui Xia:
Dual-Source Energy Cooperative Harvesting Circuit with Single Inductor. 1-4 - Haruo Kobayashi, Kosuke Machida, Yuto Sasaki, Yusuke Osawa, Pengfei Zhang, Lei Sha, Yuki Ozawa, Anna Kuwana:
Fine Time Resolution TDC Architectures -Integral and Delta-Sigma Types. 1-4 - Jinsong Wei, Jilin Zhang, Xumeng Zhang, Zuheng Wu, Chunmeng Dou, Tuo Shi, Hong Chen, Qi Liu:
An Asynchronous AER Circuits with Rotation Priority Tree Arbiter for Neuromorphic Hardware with Analog Neuron. 1-4 - Haosheng Zeng, Hong Zhang, Jianping Guo:
A CMOS Half-Bridge GaN Driver with 6-30V Input Voltage Range and 5.4ns Propagation Delay. 1-4 - Dehong Lv, Heng Ma, Fuqiang Liu, Zhiliang Hong:
A curvature corrected bandgap reference with mismatch cancelling and noise reduction. 1-4 - Qiao Yuan, Huajian Zhang, Yukun Song, Chongyang Li, Xueyi Liu, Zheng Yan:
The Design and Implementation of High Speed Hybrid Radices Reconfigurable FFT Processor. 1-4 - Hejia Cai, Yan Hu, Zhiliang Hong:
A35.2 dBm CMOS RF Power Amplifier Using an 8-Way Current-Voltage Combining Transformer with Harmonic Control. 1-4 - Jinfou Xie, Shixian Li, Yun Chen, Qichen Zhang, Xiaoyang Zeng:
High throughput multi-code LDPC encoder for CCSDS standard. 1-4 - Cristine Jin Estrada, Chen Xu, Mansun Chan:
Design of Current-Assisted Photonic Demodulator (CAPD) for Time-of-Flight CMOS Image Sensor. 1-4 - Jie Li, Liyi Xiao, Hongchen Li, Lulu Liao, Chenxu Wang:
A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network. 1-4 - Yifei Wang, Xiaofei Wang, Yuekang Guo, Ting Jin:
A Low-Power 10-bit 160-MSample/s DAC in 40-nm CMOS for Baseband Wireless Transmitter. 1-4 - Liang Pang, Yifan Chai, Mengyun Yao, Yaqing Men, Xuexiang Wang, Longxing Shi:
An Accurate and Efficient Yield Analysis for SRAM dynamic metrics Using Differential Evolution Algorithm. 1-4 - Liang Qi, Sai-Weng Sin, Rui Paulo Martins:
Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications. 1-4 - Wenjie Fu, Yu Zheng, Leilei Jin, Ming Ling:
A Fast Reduction Method for Path Process Variations Without Time-Consuming Training. 1-4 - Zhenghua Gu, Wenqin Wan, Chang Wu:
Latency Minimal Scheduling with Maximum Instruction Parallelism. 1-4 - Chun Zhao, Ce Zhou Zhao, Tian Shi Zhao:
Solution Processed Metal Oxide in Emerging Electronic Devices. 1-4 - Jia-Qiang Li, Li-Yi Xiao, Liu He, Hao-Tian Wu:
A Method to Design 5-Bit Burst Error Correction Code against the Multiple Bit Upset (MBU) in Memories. 1-4 - Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu:
Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing. 1-4 - Yalong Pang, Shuai Jiang, Lu-yuan Wang, Weiwei Liu, Ji-yang Yu, Yuehua Niu:
A Lightweight Slave-Module Interface Core to Implement IEEE 1149.5 MTM-Bus Based on FPGA. 1-4 - Zekun Zhou, Zhengyang Jin, Jianwen Cao, Bo Zhang, Yue Shi:
An On-Time Generator with Zero Quiescent Power Consumption Suitable for AOT Buck Converters. 1-4 - Xueyou Shi, Dahe Liu, Zhongjian Chen, Guangyi Chen, Shoudong Huang, Wengao Lu, Yacong Zhang:
A Low-Power Single-Slope based 14-bit Column-Level ADC for 384×288 Uncooled Infrared Imager. 1-4 - Ning Li, Wen-Yang Jiang, Blacksmith Wu, Kanyu Cao:
Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD Simulation. 1-4 - Qi Li, Yujun Shu, Yongzhen Chen, Jiangfeng Wu:
An Area-Efficient Multi-Rate Digital Decimator. 1-4 - Minyuan Ye, Lei He, Gengsheng Chen:
A Coarse-to-fine Classification for Motion Blur Kernel Size Estimation with Cascaded Neural Networks. 1-4 - Junshang Li, Zishang He, Yajie Qin:
Design of Asynchronous High Throughput SHA-256 Hardware Accelerator in 40nm CMOS. 1-4 - Yann Deval, Hervé Lapuyade, François Rivet:
Design of CMOS integrated circuits for radiation hardening and its application to space electronics. 1-4 - Siddharth Katare, Nagaveni Subramanya:
Configurable Hybrid Output Driver for GPIO with Wide Supply Voltage Range of 1.05V-3.70V. 1-3 - Zhiwei Zhao, Yuejun Zhang, Pengjun Wang, Huihong Zhang, Zhang Weishan:
Design of Crosstalk NAND Gate Circuit Based on Interconnect Coupling Capacitance. 1-4 - Xinning Liu, Song Jia, Hanzun Zhang:
A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator. 1-4 - Mengyuan Hua, Song Yang, Jin Wei, Zheyang Zheng, Jiabei He, Kevin J. Chen:
Reverse-Bias Stability and Reliability of Enhancement-mode GaN-based MIS-FET. 1-4 - Xiaoyu Zhang, Bin Liang, Ruiqiang Song:
Circuit-Level Soft Error Rate Evaluation Approach Considering Single-Event Multiple Transient. 1-4 - Junyao Wang, Hairui Wang, Bo Wang:
A 5-bit, 87-fs Step, Constant-Slope, Charge-Sharing-Based Encoding Digital-to-Time Converter in 130nm CMOS. 1-4 - Runsheng Wang, Zhe Zhang, Shaofeng Guo, Qingxue Wang, Dehuang Wu, Joddy Wang, Ru Huang:
OMI/TMI-based Modeling and Fast Simulation of Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits. 1-4 - Zhao Tuo, Tao Chen, Wei Li, Danyang Yang:
Method for improving energy efficiency of elliptic curve cryptography algorithm on reconfigurable symmetric cipher processor. 1-4 - Pingshun Ma, Yongzhen Chen, Jiangfeng Wu:
A Double-Latch Comparator for Multi-GS/s SAR ADCs in 28nm CMOS. 1-3 - Francis Balestra:
Nanoscale Devices for the end of the Roadmap. 1-4 - Xubo Song, Yuangang Wang, Zhihong Feng, Yuanjie Lv, Yamin Zhang, Lisen Zhang, Shixiong Liang, Xin Tan, Shaobo Dun, Dabao Yang, Zhirong Zhang:
GaN Schottky Diode Model for THz Multiplier Design with Consideration of Self-heating Effect. 1-3 - Huanlin Luo, Yunbo Liu, Hai Ren, Tiantian Zhang, Jian Wang, Jinmei Lai:
An FPGA-based log-structure Flash memory system for space exploration. 1-4 - Jian Gong, Zirun Zhao, Ziqing Wang, Yonghui Wu, Yong Cui:
A 20GS/s Track-and-Hold Amplifier based on InP DHBT Process. 1-4