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A. N. Nagamani

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2010 – 2019

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2019
[c4]
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S. S. Rekha, A. N. Nagamani:
Hardware Security-present and Future Trends. EEET 2019: 24-29
2018
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A. N. Nagamani, Chirag Ramesh, Vinod Kumar Agrawal:
Design of Optimized Reversible Squaring and Sum-of-Squares Units. Circuits Syst. Signal Process. 37(4): 1753-1776 (2018)
[j4]
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A. N. Nagamani, S. N. Anuktha, N. Nanditha, Vinod Kumar Agrawal:
A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 324-336 (2018)
[c3]
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A. N. Nagamani, Vijetha Ravichander, Madhumita Harish, Vinod Kumar Agrawal:
DFT methodologies for testing k-CNOT, Fredkin and Peres based reversible circuits. RAIT 2018: 1-6
2016
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A. N. Nagamani, S. Ashwin, B. Abhishek, Vinod Kumar Agrawal:
An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits. J. Electron. Test. 32(2): 175-196 (2016)
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A. N. Nagamani, S. Ashwin, B. Abhishek, K. V. Arjun, Vinod Kumar Agrawal:
Design and Analysis of Multiple Parameters Optimized n-Bit Reversible Magnitude Comparators. J. Circuits Syst. Comput. 25(9): 1650112:1-1650112:21 (2016)
2015
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  - conf/IEEEicics/NagamaniPHA15
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A. N. Nagamani, H. Vishnu Prasad, Rajendra S. Hathwar, Vinod Kumar Agrawal:
Design of optimized reversible multiplier for high speed DSP application. ICICS 2015: 1-5
2013
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  - journals/tcos/ThapliyalJNA13
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Himanshu Thapliyal, H. V. Jayashree, A. N. Nagamani, Hamid R. Arabnia:
Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder. Trans. Comput. Sci. 17: 73-97 (2013)
2011
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A. N. Nagamani, S. Nishchai:
Quaternary High Performance Arithmetic Logic Unit Design. DSD 2011: 148-153

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