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ORCIDJames H. Kukula
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2000 – 2009
- 2005
[c25]Per Bjesse, James H. Kukula:
Automatic generalized phase abstraction for formal verification. ICCAD 2005: 1076-1082- 2004
- [c24]Per Bjesse, James H. Kukula:
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs. DATE 2004: 156-161 - 2003
- [c23]Robert F. Damiano, James H. Kukula:
Checking satisfiability of a conjunction of BDDs. DAC 2003: 818-823 - [c22]Yunshan Zhu, James H. Kukula:
Generator-based Verification. ICCAD 2003: 146-153 - [c21]Per Bjesse, James H. Kukula, Robert F. Damiano, Ted Stanion, Yunshan Zhu:
Guiding SAT Diagnosis with Tree Decompositions. SAT 2003: 315-329 - 2002
- [c20]Edmund M. Clarke, Anubhav Gupta, James H. Kukula, Ofer Strichman:
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques. CAV 2002: 265-279 - [c19]Alfred Kölbl, James H. Kukula, Kurt Antreich, Robert F. Damiano:
Handling special constructs in symbolic simulation. DAC 2002: 105-110 - [c18]Pankaj Chauhan, Edmund M. Clarke, James H. Kukula, Samir Sapra, Helmut Veith, Dong Wang:
Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis. FMCAD 2002: 33-51 - [c17]In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley:
Simplifying Circuits for Formal Verification Using Parametric Representation. FMCAD 2002: 52-69 - [c16]Hee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple:
Combinational equivalence checking through function transformation. ICCAD 2002: 526-533 - 2001
- [j1]Adnan Aziz, James H. Kukula, Thomas R. Shiple, Jun Yuan:
Efficient control state-space search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 332-336 (2001) - [c15]Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Helmut Veith, Dong Wang:
Using Combinatorial Optimization Methods for Quantification Scheduling. CHARME 2001: 293-309 - [c14]Dong Wang, Pei-Hsin Ho, Jiang Long, James H. Kukula, Yunshan Zhu, Hi-Keung Tony Ma, Robert F. Damiano:
Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines. DAC 2001: 35-40 - [c13]Alfred Kölbl, James H. Kukula, Robert F. Damiano:
Symbolic RTL Simulation. DAC 2001: 47-52 - [c12]Dong Wang, Edmund M. Clarke, Yunshan Zhu, James H. Kukula:
Using cutwidth to improve symbolic simulation and Boolean satisfiability. HLDVT 2001: 165-170 - [c11]Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Thomas R. Shiple, Helmut Veith, Dong Wang:
Non-linear Quantification Scheduling in Image Computation. ICCAD 2001: 293- - 2000
- [c10]James H. Kukula, Thomas R. Shiple:
Building Circuits from Relations. CAV 2000: 113-123 - [c9]In-Ho Moon, James H. Kukula, Kavita Ravi, Fabio Somenzi:
To split or to conjoin: the question in image computation. DAC 2000: 23-28 - [c8]Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long:
Smart Simulation Using Collaborative Formal and Simulation Engines. ICCAD 2000: 120-126
1990 – 1999
- 1999
- [c7]In-Ho Moon, James H. Kukula, Thomas R. Shiple, Fabio Somenzi:
Least fixpoint approximations for reachability analysis. ICCAD 1999: 41-44 - 1998
- [c6]Thomas R. Shiple, James H. Kukula, Rajeev K. Ranjan:
A Comparison of Presburger Engines for EFSM Reachability. CAV 1998: 280-292 - [c5]Adnan Aziz, James H. Kukula, Thomas R. Shiple:
Hybrid Verification Using Saturated Simulation. DAC 1998: 615-618 - [c4]James H. Kukula, Thomas R. Shiple, Adnan Aziz:
Techniques for Implicit State Enumeration of EFSMs. FMCAD 1998: 469-482 - 1994
- [c3]José Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto:
Bitwise Encoding of Finite State Machines. VLSI Design 1994: 379-382 - 1991
- [c2]James H. Kukula, Srinivas Devadas:
Finite State Machine Decomposition by Transition Pairing. ICCAD 1991: 414-417
1980 – 1989
- 1988
- [c1]James H. Kukula:
Object relocation in OX. ICCD 1988: 8-10
Coauthor Index
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