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ORCIDVinod Pangracious
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2020 – today
- 2022
[c19]Vinod Pangracious
:
Blockchain Based Energy Trade. ICDCN 2022: 278-283
2010 – 2019
- 2018
- [c18]Vinod Pangracious, Ranjitha Dash, Ashok Kumar Turuk:
3D-cool: Design and development of adaptive thermal-aware three-dimensional NoC-based multiprocessor chip. COOL CHIPS 2018: 1-3 - 2017
- [j5]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez:
Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support. Turkish J. Electr. Eng. Comput. Sci. 25: 2044-2054 (2017) - [c17]Ranjita Kumari Dash, Vinod Pangracious, José L. Risco-Martín, Ashok Kumar Turuk, Amartya Majumdar, José Luis Ayala:
Thermal Management in 3D Homogeneous NoC Systems Using Optimized Placement of Liquid Microchannels. MCSoC 2017: 37-44 - [c16]Larbi Boubchir, Boubaker Daachi, Vinod Pangracious:
A review of feature extraction for EEG epileptic seizure detection and classification. TSP 2017: 456-460 - 2016
- [j4]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez:
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. Microprocess. Microsystems 40: 16-26 (2016) - [j3]Vinod Pangracious, Mulhim Al-Doori:
Novel Three-Dimensional Embedded FPGA Technology and Achitecture. SIGARCH Comput. Archit. News 44(4): 50-55 (2016) - [c15]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Habib Mehrez, Mohamed Abid:
Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance. PDP 2016: 635-642 - 2015
- [b1]Vinod Pangracious, Zied Marrakchi, Habib Mehrez:
Three-Dimensional Design Methodologies for Tree-based FPGA Architecture. Lecture Notes in Electrical Engineering 350, Springer 2015, ISBN 978-3-319-19173-7, pp. 1-209 - [j2]Vinod Pangracious, Zied Marrakchi, Habib Mehrez:
Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA. IEEE Micro 35(6): 48-59 (2015) - [c14]Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid:
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. ARC 2015: 411-418 - 2014
- [j1]Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez:
Architecture level optimization of 3-dimensional tree-based FPGA. Microelectron. J. 45(4): 355-366 (2014) - [c13]Sonda Chtourou, Mohamed Abid, Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez:
Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. 3DIC 2014: 1-7 - [c12]Vinod Pangracious, Zied Marrakchi, Nizar Beltaief, Habib Mehrez, Umer Farooq:
Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA. DTIS 2014: 1-6 - [c11]Vinod Pangracious, Mohamed Sahbi Marrakchi, Habib Mehrez, Zied Marrakchi:
On wiring delays reduction of tree-based FPGA using 3-D fabric. SoCC 2014: 64-69 - 2013
- [c10]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. 3DIC 2013: 1-8 - [c9]Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez:
Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. ARC 2013: 197-209 - [c8]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Architecture level TSV count minimization methodology for 3D tree-based FPGA. COOL Chips 2013: 1-3 - [c7]Vinod Pangracious, Habib Mehrez, Umer Farooq, Zied Marrakchi:
High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA). FPGAworld 2013: 3:1-3:6 - [c6]Vinod Pangracious, Zied Marrakchi, Habib Mehrez:
Design and optimization of heterogeneous tree-based FPGA using 3D technology. FPT 2013: 334-337 - [c5]Vinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi:
Physical design exploration of 3D tree-based FPGA architecture. ACM Great Lakes Symposium on VLSI 2013: 335-336 - [c4]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
TSV count minimization and thermal analysis for 3D Tree-based FPGA. ICICDT 2013: 223-226 - [c3]Vinod Pangracious, Habib Mehrez, Zied Marrakchi:
Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis. NEWCAS 2013: 1-4 - [c2]Vinod Pangracious, Habib Mehrez, Nizar Beltaief, Zied Marrakchi, Umer Farooq:
Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). ReConFig 2013: 1-6 - 2012
- [i3]Ramya Menon C., Vinod Pangracious:
A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs. CoRR abs/1201.3332 (2012) - [i2]Ramya Menon C., Vinod Pangracious:
Thermal analysis & optimization of a 3 dimensional heterogeneous structure. CoRR abs/1203.1799 (2012) - 2011
- [i1]Annmol Cherian, Ajay Augustine, Jemy Jose, Vinod Pangracious:
A Novel Methodology for Thermal Analysis & 3-Dimensional Memory Integration. CoRR abs/1109.0708 (2011)
2000 – 2009
- 2009
- [c1]José L. Ayala, Arvind Sridhar, Vinod Pangracious, David Atienza, Yusuf Leblebici:
Through Silicon Via-Based Grid for Thermal Control in 3D Chips. NanoNet 2009: 90-98
Coauthor Index
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