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ORCIDHironori Nakajo
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2020 – today
- 2023
[c53]Masashi Takemoto
, Yasutake Masuda, Jingyong Cai, Hironori Nakajo:
Learning Algorithm for LesserDNN, a DNN with Quantized Weights. SoICT 2023: 1-7- 2022
- [c52]Hidetaro Tanaka, Tomoaki Tanaka, Ryosuke Higashi, Tsutomu Sekibe, Shuichi Takada, Hironori Nakajo:
Implementation of a RISC-V SMT Core in an AI processor. SoICT 2022: 15-22 - 2021
- [j12]Hironori Nakajo:
Editor's Message to Special Issue of Embedded Systems Engineering. J. Inf. Process. 29: 215 (2021) - 2020
- [j11]Daichi Teruya, Hironori Nakajo:
A Ruby-Based Hardware/Software Co-Design Environment with Functional Reactive Programming: Mulvery. IEICE Trans. Inf. Syst. 103-D(9): 1929-1938 (2020) - [j10]Hironori Nakajo:
Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. 28: 123 (2020) - [j9]Hironori Nakajo:
Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. 28: 394 (2020)
2010 – 2019
- 2019
- [j8]Hironori Nakajo:
Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. 27: 135 (2019) - [c51]Kesevan Veloo, Hayate Kojima, Shogo Takata, Masashi Nakamura, Hironori Nakajo:
Interactive Cultivation System for the Future IoT-Based Agriculture. CANDAR Workshops 2019: 298-304 - [c50]Ryota Yamashita, Daichi Teruya, Hironori Nakajo:
Parallelization of Recursive Function in Ruby-Based High-Level Synthesis. FPT 2019: 407-410 - [c49]Tran Viet Toan, Rin Nishikawa, Le Tien Thanh, Masashi Takemoto, Tran Van Hoai, Huynh Thi Thanh Binh, Hironori Nakajo:
Cow estrus detection with low-frequency accelerometer sensor by unsupervised learning. SoICT 2019: 342-349 - 2018
- [j7]Hironori Nakajo:
Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. 26: 539 (2018) - [j6]Yo Nishiyama, Yuko Sasaki, Yuki Hirai, Hironori Nakajo, Keiichi Kaneko:
Fault-tolerant Routing based on Routing Capabilities in a Hyper-Star Graph. J. Inf. Sci. Eng. 34(6): 1353-1366 (2018) - [c48]Jingyong Cai, Masashi Takemoto, Hironori Nakajo:
Implementation of DNN on a RISC-V Open Source Microprocessor for IoT devices. GCCE 2018: 295-299 - [c47]Jingyong Cai, Masashi Takemoto, Hironori Nakajo:
A Deep Look into Logarithmic Quantization of Model Parameters in Neural Networks. IAIT 2018: 6:1-6:8 - [c46]Yusuke Katoh, Hironari Yoshiuchi, Yoshio Murata, Hironori Nakajo:
Operation in Partitioned Circuits with Scalable Hardware Mechanism. JCSSE 2018: 1-6 - [c45]Le Tien Thanh, Rin Nishikawa, Masashi Takemoto, Huynh Thi Thanh Binh, Hironori Nakajo:
Cow estrus detection via Discrete Wavelet Transformation and Unsupervised Clustering. SoICT 2018: 305-312 - 2017
- [c44]Masashi Takemoto, Ryota Suzuki, Katsuhiko Umeno, Masayuki Yashiro, Tetsuya Ryuchi, Kohta Ohshima, Naoya Kitagawa, Hironori Nakajo:
Performance evaluation of an SoC for the real-time lens-free imager RALFIE. GCCE 2017: 1-4 - [c43]Yuto Ishikawa, Keitaro Yanai, Keisuke Koike, Takefumi Miyoshi, Hironori Nakajo:
Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool. HEART 2017: 8:1-8:6 - 2016
- [c42]Masashi Takemoto, Ryota Suzuki, Katsuhiko Umeno, Masayuki Yashiro, Tetsuya Ryuchi, Kohta Ohshima, Naoya Kitagawa, Hironori Nakajo:
Design of real-time advanced lens free imager. SoICT 2016: 411-416 - 2011
- [j5]Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo:
Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis. IEICE Trans. Inf. Syst. 94-D(12): 2328-2337 (2011) - [c41]Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitkänen, Juha Röning:
Detecting water waste activities for water-efficient living. UbiComp 2011: 579-580 - [c40]Hironori Nakajo, Keisuke Koike, Atsushi Ohta, Kohta Ohshima, Kaori Fujinami:
Reconfigurable Android with an FPGA Accelerator for the Future Embedded Devices. ICNC 2011: 173-178 - [c39]Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitkänen, Juha Röning:
Feature Selection and Activity Recognition to Detect Water Waste from Water Tap Usage. RTCSA (2) 2011: 138-141 - [c38]Noboru Tanabe, Boonyasitpichai Nuttapon, Hironori Nakajo, Yuka Ogawa, Junko Kogou, Masami Takata, Kazuki Joe:
A memory accelerator with gather functions for bandwidth-bound irregular applications. IA3@SC 2011: 35-42 - 2010
- [j4]Noboru Tanabe, Hirotaka Hakozaki, Hiroshi Ando, Yasunori Dohi, Zhengzhe Luo, Hironori Nakajo:
An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing. J. Supercomput. 51(3): 279-309 (2010) - [c37]Hiroki Yokoyama, Yuhei Horibe, Peng Zhang, Shinobu Miwa, Hironori Nakajo:
An Effective Replacement Policy Focusing on Lifetime of a Cache Line. CDES 2010: 146-152 - [c36]Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo:
Parallelizing Hilbert-Huang Transform on a GPU. ICNC 2010: 184-190 - [c35]Noboru Tanabe, Hironori Nakajo:
Acceleration for MPI derived datatypes using an enhancer of memory and network. IPDPS Workshops 2010: 1-6
2000 – 2009
- 2009
- [c34]Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo:
Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. CDES 2009: 171-177 - [c33]Yoshiyasu Ogasawara, Hironori Nakajo:
An Effective Replacement Strategy of Cache Memory for an SMT Processor. DSD 2009: 19-25 - [c32]Noboru Tanabe, Atsushi Ohta, Pulung Waskito, Hironori Nakajo:
Network Interface Architecture for Scalable Message Queue Processing. ICPADS 2009: 268-275 - [c31]Noboru Tanabe, Manami Sasaki, Hironori Nakajo, Masami Takata, Kazuki Joe:
The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing. PDPTA 2009: 427-433 - 2008
- [c30]Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita:
Low-Complexity Bypass Network Using Small RAM. CDES 2008: 153-159 - [c29]Noboru Tanabe, Hironori Nakajo:
An Enhancer of Memory and Network for Cluster and its Applications. PDCAT 2008: 99-106 - [c28]Noboru Tanabe, Hironori Nakajo:
Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network. PVM/MPI 2008: 324-325 - 2007
- [j3]Kenji Kise, Toshinori Sato, Hironori Nakajo:
Introduction. SIGARCH Comput. Archit. News 35(5): 1-2 (2007) - [c27]Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano:
Performance evaluation on low-latency communication mechanism of DIMMnet-2. Parallel and Distributed Computing and Networks 2007: 57-62 - [c26]Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo:
Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. PDPTA 2007: 787-793 - [c25]Satoshi Watanabe, Yoshiyasu Ogasawara, Ippei Tate, Hirofumi Yano, Hironori Nakajo:
Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices. PDPTA 2007: 794-800 - 2006
- [c24]Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe:
DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. FPL 2006: 1-4 - [c23]Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki:
Implementation of PC Cluster System with Memory Mapped File by Commodity OS. PDPTA 2006: 902-908 - [c22]Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo:
A Model of Implementable SMT Processor on FPGA. PDPTA 2006: 909-915 - [c21]Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo:
Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA 2006: 916-924 - 2005
- [c20]Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano:
Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. ISHPC 2005: 211-218 - [c19]Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo:
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. PDCAT 2005: 778-780 - [c18]Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo:
A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA 2005: 447-453 - [c17]Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki:
Development of a Thread Scheduler for SMT Processor Architecture. PDPTA 2005: 454-460 - [c16]Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo:
A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. PDPTA 2005: 461-467 - 2004
- [c15]Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano:
A New Memory Module for Memory Intensive Applications. PARELEC 2004: 123-128 - [c14]Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo:
Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA 2004: 317-323 - 2003
- [c13]Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki:
Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA 2003: 609-615 - [c12]Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki:
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA 2003: 1669-1675 - [c11]Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki:
Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA 2003: 1775-1781 - 2002
- [j2]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Clust. Comput. 5(1): 7-17 (2002) - [c10]Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano:
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. PARELEC 2002: 9-14 - 2000
- [j1]Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda:
A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links. Int. J. Parallel Program. 28(2): 179-194 (2000) - [c9]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
MEMOnet : Network interface plugged into a memory slot. CLUSTER 2000: 17-16 - [c8]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN 2000: 186-194 - [c7]Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano:
Coherence Protocol for Home Proxy Cache on RHiNET. PDPTA 2000
1990 – 1999
- 1998
- [c6]Hironori Nakajo, Hidekazu Tanaka, Yoshinori Nakanishi, Masaki Kohata, Yukio Kaneda:
Distributed Shared-Memory for a Workstation Cluster with a High Speed Serial Interface. HPCN Europe 1998: 588-597 - 1997
- [c5]Hironori Nakajo, Satoshi Ohtani, Takashi Matsumoto, Masadi Kohata, Kei Hiraki, Yukio Kaneda:
An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. International Conference on Supercomputing 1997: 253-260 - [c4]Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda:
An Implementation and Evaluation of a Distributed Shared-Memory System on Workstation Clusters Using Fast Serial Links. ISHPC 1997: 143-158 - 1996
- [c3]Hironori Nakajo, Satoshi Ohtani, Yukio Kaneda:
A Simulation-based Evaluation of a Disk I/O Subsystem for a Massively Parallel Computer: JUMP-1. ICDCS 1996: 562-569 - 1995
- [c2]Hironori Nakajo, Takashi Matsumoto, Masaki Kohata, Hideo Matsuda, Kei Hiraki, Yukio Kaneda:
High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. Parallel and Distributed Computing and Systems 1995: 470-473 - 1994
- [c1]Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori:
Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. ISPAN 1994: 427-434
Coauthor Index
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