• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 188 matches

• 2024
• 
  Jhilam Jana, Ritesh Sur Chowdhury, Sayan Tripathi, Jaydeb Bhaumik:
  FPGA implementation of compact and low-power multiplierless architectures for DWT and IDWT. J. Real Time Image Process. 21(1): 19 (2024)
• 
  Elivander J. T. Pereira, Dayan Adionel Guimarães, Rahul Shrestha:
  VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. 71(5): 2348-2361 (2024)
• 
  Vincent Abbott:
  Neural Circuit Diagrams: Robust Diagrams for the Communication, Implementation, and Analysis of Deep Learning Architectures. Trans. Mach. Learn. Res. 2024 (2024)
• 
  Corinna Giebler, Christoph Gröger, Eva Hoos, Holger Schwarz, Bernhard Mitschang:
  Implementation Patterns for Zone Architectures in Enterprise-Grade Data Lakes. CAiSE 2024: 267-283
• 
  Francesco Giovinazzo, Alessandro Perri, Marco Staiano, Francesco Grella, Marco Sartore, Manuela Adami, Riccardo Galletti, Giorgio Cannata:
  Design, Implementation and Testing of an EtherCAT-based Network for Multi-modal Distributed Sensing Architectures. CASE 2024: 830-837
• 
  Ayan Palchaudhuri, Anindya Sundar Dhar:
  FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. VLSID 2024: 617-622
• 
  Vincent Abbott:
  Neural Circuit Diagrams: Robust Diagrams for the Communication, Implementation, and Analysis of Deep Learning Architectures. CoRR abs/2402.05424 (2024)
• 2023
• 
  Kiran Kumar Bhadavath, Z. Mary Livinsa:
  Very large scale integration implementation of efficient finite impulse response filter architectures using novel distributed arithmetic for digital channelizer of software defined radio. Int. J. Circuit Theory Appl. 51(3): 1153-1167 (2023)
• 
  Madeleine Abernot, Aida Todri-Sanial:
  Simulation and implementation of two-layer oscillatory neural networks for image edge detection: bidirectional and feedforward architectures. Neuromorph. Comput. Eng. 3(1): 14006 (2023)
• 
  Gregorio Quintana-Ortí, Fernando Hernando, Francisco D. Igual:
  Algorithm 1033: Parallel Implementations for Computing the Minimum Distance of a Random Linear Code on Distributed-memory Architectures. ACM Trans. Math. Softw. 49(1): 8:1-8:24 (2023)
• 
  Naifeng Zhang, Austin Ebel, Negar Neda, Patrick Brinich, Benedict Reynwar, Andrew G. Schmidt, Mike Franusich, Jeremy Johnson, Brandon Reagen, Franz Franchetti:
  Generating High-Performance Number Theoretic Transform Implementations for Vector Architectures. HPEC 2023: 1-7
• 
  Adrian German, Marcelo Pias, Qiao Xiang:
  On the Design and Implementation of a Quantum Architectures Knowledge Unit for a CS Curriculum. SIGCSE (1) 2023: 1150-1156
• 2022
• 
  Mohamed Najoui, Mounir Bahtat, Abdessamad Klilou, Anas Hatim, Said Belkouch, Atman Jbari, Noureddine Chabini:
  Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures. Comput. Electr. Eng. 102: 108294 (2022)
• 
  Nikolay M. Evstigneev, Oleg I. Ryabkov, A. N. Bocharov, V. P. Petrovskiy, I. O. Teplyakov:
  Compensated summation and dot product algorithms for floating-point vectors on parallel architectures: Error bounds, implementation and application in the Krylov subspace methods. J. Comput. Appl. Math. 414: 114434 (2022)
• 
  Dimitris Theodoropoulos, Nektarios Kranitis, Antonis M. Paschalis, Elias Machairas, Antonios Paschalis:
  Efficient Hardware Architectures and Implementations of Packet-Level Erasure Coding Schemes for High Data Rate Reliable Satellite Communications. IEEE Trans. Aerosp. Electron. Syst. 58(3): 2269-2280 (2022)
• 
  Kamil Stokfiszewski, Kamil Wieloch, Mykhaylo Yatsymirskyy:
  An efficient implementation of one-dimensional discrete wavelet transform algorithms for GPU architectures. J. Supercomput. 78(9): 11539-11563 (2022)
• 
  Zheang Huai, Jingbo Zhou, Xinmiao Zhang:
  Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime. J. Signal Process. Syst. 94(10): 1067-1082 (2022)
• 
  Inês Araújo Machado, Carlos Costa, Maribel Yasmina Santos:
  Advancing Data Architectures with Data Mesh Implementations. CAiSE Forum 2022: 10-18
• 
  Federico Di Menna, Henry Muccini, Karthik Vaidhyanathan:
  FEAST: a framework for evaluating implementation architectures of self-adaptive IoT systems. SAC 2022: 1440-1447
• 2021
• 
  Jin Tack Lim:
  The Design, Implementation, and Evaluation of Software and Architectural Support for Nested Virtualization on Modern Architectures. Columbia University, USA, 2021
• 
  Muhammad Usman, Waseem Ahmad, Alvis Cheuk Ming Fong:
  Design and Implementation of a System for Comparative Analysis of Learning Architectures for Churn Prediction. IEEE Commun. Mag. 59(9): 86-90 (2021)
• 
  Candelaria Mosquera, Facundo Nahuel Diaz, Fernando Binder, Jose Martin Rabellino, Sonia Elizabeth Benítez, Alejandro Daniel Beresñak, Alberto Seehaus, Gabriel Ducrey, Jorge Alberto Ocantos, Daniel Roberto Luna:
  Chest x-ray automated triage: A semiologic approach designed for clinical implementation, exploiting different types of labels through a combination of four Deep Learning architectures. Comput. Methods Programs Biomed. 206: 106130 (2021)
• 
  Bartlomiej Kotyra, Lukasz Chabudzinski, Przemyslaw Stpiczynski:
  High-performance parallel implementations of flow accumulation algorithms for multicore architectures. Comput. Geosci. 151: 104741 (2021)
• 
  Emanuel Trunzer, Birgit Vogel-Heuser, Jan-Kristof Chen, Moritz Kohnle:
  Model-Driven Approach for Realization of Data Collection Architectures for Cyber-Physical Systems of Systems to Lower Manual Implementation Efforts. Sensors 21(3): 745 (2021)
• 
  Issaku Kanamori, Ken-Ichi Ishikawa, Hideo Matsufuru:
  Object-Oriented Implementation of Algebraic Multi-grid Solver for Lattice QCD on SIMD Architectures and GPU Clusters. ICCSA (5) 2021: 218-233
• 
  Tero Partanen, Ari Lemmetti, Panu Sjövall, Jarno Vanne:
  High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding. ISCAS 2021: 1-5
• 
  Vu Truong-Tuan, Chi Hoang-Phuong, Anh Pham-Tuan, Phuc Pham-Hong, Quang Hieu Dang, Hoang Nguyen-Huy, Minh Nguyen-Duc:
  FPGA Implementation of Parallel Neurosynaptic Cores for Neuromorphic Architectures. NEWCAS 2021: 1-4
• 2020
• 
  Alberto J. Alvares, Efrain Andres Rodriguez Gasca, Cristhian I. R. Jaimes, Juan S. Toquica, João C. E. Ferreira:
  STEP-NC Architectures for Industrial Robotic Machining: Review, Implementation and Validation. IEEE Access 8: 152592-152610 (2020)
• 
  Vijay Dahiphale, Gaurav Bansod, Ankur Zambare, Narayan Pisharoty:
  Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA. Frontiers Inf. Technol. Electron. Eng. 21(4): 615-628 (2020)
• 
  Gomathi Swaminathan, G. Murugesan, S. Sasikala, L. Murali:
  A novel implementation of combined systolic and folded architectures for adaptive filters in FPGA. Microprocess. Microsystems 74: 103018 (2020)

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