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Publication search results
found 146 matches
- 2008
- Erkan Acar, Sule Ozev, Ganesh Srinivasan, Friedrich Taenzler:
Optimized EVM Testing for IEEE 802.11a/n RF ICs. ITC 2008: 1-10 - Brice Achkir, Pavel Zivny, Bill Eklow:
Parametric Testing of Optical Interfaces. ITC 2008: 1 - Ernst Aderholz, Heiko Ahrens, Michael Rohleder:
Bridging the gap between Design and Test Engineering for Functional Pattern Development. ITC 2008: 1-10 - Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra:
Optimized Circuit Failure Prediction for Aging: Practicality and Promise. ITC 2008: 1-10 - Heiko Ahrens, Rolf Schlagenhaft, Helmut Lang, V. Srinivasan, Enrico Bruzzano:
DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG. ITC 2008: 1-10 - Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georg Mueller:
Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs. ITC 2008: 1-10 - Waleed K. Al-Assadi, Sindhu Kakarla:
Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits. ITC 2008: 1-9 - Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Zainalabedin Navabi:
NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure. ITC 2008: 1 - Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi:
"Plug & Test" at System Level via Testable TLM Primitives. ITC 2008: 1-10 - Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn:
Hardware-based Error Rate Testing of Digital Baseband Communication Systems. ITC 2008: 1-10 - Sobeeh Almukhaizim, Ozgur Sinanoglu:
Peak Power Reduction Through Dynamic Partitioning of Scan Chains. ITC 2008: 1-10 - Sadok Aouini, Gordon W. Roberts:
Generating Test Signals for Noise-Based NPR/ACPR Type Tests in Production. ITC 2008: 1-9 - Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki:
Hardware Overhead Reduction for Memory BIST. ITC 2008: 1 - Swapnil Bahl, Rajiv Sarkar, Akhil Garg:
Low Power Test. ITC 2008: 1 - Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir:
Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained. ITC 2008: 1-10 - Paolo Bernardi, Fabio Melchiori, Davide Pandini, Santo Pugliese, Davide Appello:
Robust Design-for-Productization Practices for High Quality Automotive Products. ITC 2008: 1-9 - Sounil Biswas, Ronald D. Blanton:
Improving the Accuracy of Test Compaction through Adaptive Test Update. ITC 2008: 1 - Surendra Bommu, Kameshwar Chandrasekar, Rahul Kundu, Sanjay Sengupta:
CONCAT: CONflict Driven Learning in ATPG for Industrial designs. ITC 2008: 1-10 - William J. Bowhers:
FPGA Time Measurement Module: Preliminary Results. ITC 2008: 1 - Kenneth M. Butler, John M. Carulli Jr., Jayashree Saxena:
Modeling Test Escape Rate as a Function of Multiple Coverages. ITC 2008: 1-9 - Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella:
On-line Failure Detection in Memory Order Buffers. ITC 2008: 1-10 - Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen:
Testing Methodology of Embedded DRAMs. ITC 2008: 1-9 - Che-Jen Jerry Chang, Takeo Kobayashi:
Test Quality Improvement with Timing-aware ATPG: Screening small delay defect case study. ITC 2008: 1 - Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen:
Transition Test on UltraSPARC- T2 Microprocessor. ITC 2008: 1-10 - Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula:
A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. ITC 2008: 1-10 - Geng-Ming Chiu, James Chien-Mo Li:
IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores. ITC 2008: 1 - Brandon Chu:
Solder Bead on High Density Interconnect Printed Circuit Board. ITC 2008: 1-5 - Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Scan Shift and Capture in the EDT Environment. ITC 2008: 1-10 - Jayant D'Souza, Subramanian Mahadevan, Nilanjan Mukherjee, Graham Rhodes, Jocelyn Moreau, Thomas Droniou, Paul Armagnat, Damien Sartoretti:
High Test Quality in Low Pin Count Applications. ITC 2008: 1 - Scott Davidson:
Justifying DFT with a Hierarchical Top-Down Cost-Benefit Model. ITC 2008: 1-10
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