default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID20th LATS 2019: Santiago, Chile
- IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019. IEEE 2019, ISBN 978-1-7281-1756-0
- Alberto Bosio, Paolo Bernardi
, Annachiara Ruospo, Ernesto Sánchez:
A Reliability Analysis of a Deep Neural Network. 1-6 - Frank Plasencia-Balabarca, Edward Mitacc-Meza, Mario Raffo-Jara, Carlos Silva Cárdenas:
A Flexible UVM-Based Verification Framework Reusable with Avalon, AHB, AXI and Wishbone Bus Interfaces for an AES Encryption Module. 1-4 - Cezar Antônio Rigo, Lucas M. Luza, Elder Dominghini Tramontin, Victor M. Goncalves Martins, Sara Vega Martínez, Leonardo Kessler Slongo, Laio Oriel Seman, Luigi Dilillo, Fabian Luis Vargas, Eduardo A. Bezerra:
A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites. 1-6 - Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek:
Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. 1-4 - Juan M. Alvarez Q., John A. Sanabria-Ordoñez, José Isidro García Melo:
Microservices-based architecture for fault diagnosis in tele-rehabilitation equipment operated via Internet. 1-6 - Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco:
NoCFI: A Hybrid Fault Injection Method for Networks-On-Chip. 1-6 - Raphael Segabinazzi Ferreira, Jörg Nolte:
Low latency reconfiguration mechanism for fine-grained processor internal functional units. 1-6 - Zhan Gao, Santosh Malagi, Erik Jan Marinissen, Joe Swenton, Jos Huisken, Kees Goossens:
Defect-Location Identification for Cell-Aware Test. 1-6 - Salem Abdennadher, Arani Sinha, Yonghyun Kim:
Analog/Mixed Signal IP DFx from a Foundry perspective. 1-4 - Rodrigo Zeli, Reinaldo Silveira, Qadeer Qureshi:
SoC Memory Test Optimization using NXP MTR Solutions. 1-5 - Abhishek Das, Nur A. Touba:
Online Correction of Hard Errors and Soft Errors via One-Step Decodable OLS Codes for Emerging Last Level Caches. 1-6 - Ghazanfar Ali, Jerrin Pathrose, Hans G. Kerkhoff:
IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time. 1-6 - Luiz G. S. Dias, Carlos J. González, Fernando J. Boeira, Tiago R. Balen:
Electromagnetic Immunity Test of Analog-to-Digital Interfaces of a Mixed-Signal Programmable SoC. 1-5 - Estevan Lara, Guilherme Debon, Roger C. Goerl, Paulo Ricardo Cechelero Villa, Dorian Schramm, Leticia B. Poehls, Fabian Vargas:
A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture. 1-6 - Alexander Aponte-Moreno, Felipe Restrepo-Calle, Cesar Augusto Pedraza:
MiFIT: A Fault Injection Tool to Validate the Reliability of Microprocessors. 1-5 - Thiago Santos Copetti, Tiago R. Balen, E. Brum, C. Aquistapace, Leticia Bolzani Poehls:
A Comparative Study Between FinFET and CMOS-Based SRAMs under Resistive Defects. 1-6 - Douglas Rossi de Melo, César Albenes Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra:
Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. 1-6 - Vladimir Hahanov, Wajeb Gharibi, Eugenia Litvinova, Svetlana Chumachenko:
Qubit-driven Fault Simulation. 1-7 - Alexander Aponte-Moreno, Cesar Augusto Pedraza, Felipe Restrepo-Calle:
Reducing Overheads in Software-based Fault Tolerant Systems using Approximate Computing. 1-6 - Marwan Ammar, Ghaith Bany Hamad, Otmane Aït Mohamed:
Probabilistic High-Level Estimation of Vulnerability and Fault Mitigation of Critical Systems Using Fault-Mitigation Trees (FMTs). 1-6 - Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
Mixed-level identification of fault redundancy in microprocessors. 1-6 - Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. 1-4 - Daniel H. P. Kraak, Cemil Cem Gürsoy, Innocent O. Agbo, Mottaqiallah Taouil, Maksim Jenihhin, Jaan Raik, Said Hamdioui:
Software-Based Mitigation for Memory Address Decoder Aging. 1-6 - Matheus Monteiro Mariano, Érica Ferreira de Souza, André Takeshi Endo, Nandamudi L. Vijaykumar:
Analyzing graph-based algorithms employed to generate test cases from finite state machines. 1-6 - Daniel Sánchez, Pablo A. Ferreyra, Juan A. Fraire, Fabian Gomez, Raoul Velazco, Dardo Vinas Viscardi:
A Wireless Embedded System for Measuring the Effects of Ionizing Radiations. 1-6 - Enrique Alvarez-Fontecilla, Angel Abusleme:
A Non-Linearity Compensation Technique for Charge-Redistribution SAR ADCs. 1-4 - Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac:
A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. 1-6 - Alejandro Serrano-Cases, Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez:
Softerror mitigation for multi-core processors based on thread replication. 1-5 - Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu:
Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model. 1-6 - Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler:
Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements. 1-4 - Walter J. Lancioni, Pablo A. Petrashin, Luis E. Toledo, Carlos Vazquez, Juan Luis Castagnola, Fortunato Carlos Dualibe:
OBT applied to a 2nd order continuous time Feedforward Sigma Delta modulator. 1-4 - Pablo A. Ferreyra, Juan A. Fraire, Fabian Gomez, Raoul Velazco, Daniel Sánchez, Dardo Vinas Viscardi:
Delay-Tolerant Wireless Networks on Chip: Preliminary Analysis and Results. 1-6 - Ayman A. Atallah, Ghaith Bany Hamad, Otmane Aït Mohamed:
Reliability Analysis of TSN Networks Under SEU Induced Soft Error Using Model Checking. 1-6 - Ivan D. Meza-Ibarra, Víctor H. Champac, Roberto Gómez-Fuentes, Jose R. Noriega-Luna, A. Vera-Marquina:
Identification of Logic Paths Influenced by Severe Coupling Capacitances. 1-6 - Martin Krcma, Zdenek Kotásek, Jakub Lojda:
Detecting hard synapses faults in artificial neural networks. 1-6 - Karel Szurman, Zdenek Kotásek:
Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. 1-4 - Hassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Francois Lefevre:
Use of ensemble methods for indirect test of RF circuits: can it bring benefits? 1-6 - Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone:
On the evaluation of SEU effects in GPGPUs. 1-6 - Fabio Benevenuti, Fernanda Lima Kastensmidt:
Comparing Exhaustive and Random Fault Injection Methods for Configuration Memory on SRAM-based FPGAs. 1-6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-01 20:31 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
