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ORCID18. VDAT 2014: Coimbatore, India
- 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, India, July 16-18, 2014. IEEE 2014, ISBN 978-1-4799-5088-1
- Sreehari Rao Patri, Suresh Alapati, Surendra Chowdary, K. S. R. Krishna Prasad:
250mA ultra low drop out regulator with high slew rate double recycling folded cascode error amplifier. 1-5 - Sanjay Singh
, Sumeet Saurav, Ravi Saini, Anil K. Saini, Chandra Shekhar, Anil Vohra:
Automatic real-time extraction of focused regions in a live video stream using edge width information. 1-2 - Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar:
Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers. 1-6 - Partha De, Kunal Banerjee, Chittaranjan A. Mandal:
A BDD based secure hardware design method to guard against power analysis attacks. 1-2 - Mohammad Shueb Romi, Naushad Alam, Mohd Yusuf Yasin:
An analytical delay model for CMOS Inverter-Transmission Gate structure. 1-6 - Deep Kishore Parsediya, Jawar Singh, Pavan Kumar Kankar:
Modeling and simulation of variable thickness based stepped MEMS cantilever designs for biosensing and pull-in voltage optimization. 1-2 - Sabyasachee Banerjee, Subhashis Majumder:
A thermal aware 3D IC partitioning technique. 1-6 - Pranav Narayan Gour, Sujay Narumanchi, Sumeet Saurav, Sanjay Singh:
Hardware accelerator for real-time image resizing. 1-6 - Srinivasa Reddy Kotha, Sumit Bajaj, Sahoo Subhendu Kumar:
An LUT based RNS FIR filter implementation for reconfigurable applications. 1-6 - Radhamanjari Samanta, Adil I. Erzin, Soumyendu Raha:
Timing-driven Steiner tree construction on uniform λ-geometry. 1-4 - M. E. Jayasanthi Ranjith, N. J. R. Muniraj:
VLSI implementation of novel fast confluence ICA algorithm for signal processing applications. 1-2 - Sumit Saha, Bapi Kar, Susmita Sur-Kolay:
A novel architecture for QPSK modulation based on time-mode signal processing. 1-6 - Pratik Dutta, Chandan Bandyopadhyay, Hafizur Rahaman:
All optical implementation of Mach-Zehnder interferometer based reversible sequential circuit. 1-2 - Somak Das, Sowvik Dey:
Design of a fault tolerant low-order interleaved memory based on the concept of bubble-stack an image storage perspective. 1-6 - Ekta Prajapati, Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma:
Operation-aware assist circuit design for improved write performance of FinFET based SRAM. 1-6 - Mamata Panigrahy, Indrajit Chakrabarti, Anindya Sundar Dhar:
VLSI design of fast fractal image encoder. 1-2 - Venkata Ganapathi Puppala:
A VLIW-Vector co-processor design for accelerating Basic Linear Algebraic Operations in OpenCV. 1-6 - P. Saravanan, P. Kalpana, V. Prcethisri, V. Sneha:
Power analysis attack using neural networks with wavelet transform as pre-processor. 1-6 - Soumya J., Ashish Sharma, Santanu Chattopadhyay:
A locally reconfigurable Network-on-Chip architecture and application mapping onto it. 1-6 - Kasturi Subramanyam, Sadulla Shaik, Ramesh Vaddi:
Tunnel FET based low voltage static vs dynamic logic families for energy efficiency. 1-2 - R. R. Manikandan, Venkata Narayana Rao Vanukuru, Anjan Chakravorty, Bharadwaj S. Amrutur:
Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductors. 1-6 - Prateek Thakyal, Prabhat Mishra:
Layout-aware signal selection in reconfigurable architectures. 1-6 - Vivek Kumar, Vinay B. Y. Kumar, Sachin B. Patkar:
FPGA-based implementation of M4RM for matrix multiplication over GF(2). 1-2 - Jai Gopal Pandey, Arindam Karmakar, S. Gurunarayanan:
Architectures and algorithms for image and video processing using FPGA-based platform. 1 - Vimal Kumar Singh Yadav, Ratul Kr. Baruah:
An analytic potential and threshold voltage model for short-channel symmetric double-gate MOSFET. 1-2 - Swagata Saha Sau, Rajat Kumar Pal:
A re-router for optimizing wire length in two-and four-layer no-dogleg channel routing. 1-6 - Pranay Samanta, Deepak Chauhan, Sujay Deb, Piyush Kumar Gupta:
UVM based STBUS verification IP for verifying SoC architectures. 1-2 - Narendra Kumar Meena, Hemangee K. Kapoor, Shounak Chakraborty:
A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip. 1-6 - Indrajit Das, Manodipan Sahoo, Pranab Roy, Hafizur Rahaman:
A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications. 1-6 - Rimpy Bishnoi, Pankaj Kumar Srivastava, Vijay Laxmi, Manoj Singh Gaur, Apoorva Sikka:
Distributed adaptive routing for spidergon NoC. 1-6 - Antony Xavier Glittas, Gopalakrishnan Lakshminarayanan:
Pipelined FFT architectures for real-time signal processing and wireless communication applications. 1-2 - Manash Chanda, Ananda Sankar Chakraborty, S. Nag, Raina Modak:
Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application. 1-2 - Bijay Kumar Dalai, N. Karnnan, Arvind Kumar Sharma, Bulusu Anand:
An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect. 1-2 - Ramesh Bhakthavatchalu, Sreeja Krishnan, V. Vineeth, M. Nirmala Devi:
Deterministic seed selection and pattern reduction in Logic BIST. 1-2 - Srinivasa Reddy Kotha, Devendra Bilaye, Utkarsh Jain, Sahoo Subhendu Kumar:
An approach for efficient FIR filter design for hearing aid application. 1-5 - P. Saidesh Kumar, M. A. Seenivasan:
A 32×32 CMOS image sensor: Tested using process and temperature compensated voltage controlled current source. 1-6 - Debayan Bairagi, Soumya Pandit:
Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications. 1-6 - Swarnendu Ray, Arnab Sarkar:
A Pseudo-Deadline Based O(1) proportional share scheduler for embedded systems. 1-2 - Amitava Ghosh, Anindya Sundar Dhar, Achintya Halder:
An ultra low power MICS/ISM band transmitter in 0.18 μm CMOS. 1-6 - Arighna Deb, Debesh Kumar Das:
A regular network of symmetric functions in quantum-dot cellular automata. 1-6 - Rohan Sinha, Mohammad S. Hashmi, G. Anil Kumar:
A positive level shifter for high speed symmetric switching in flash memories. 1-5 - Navonil Chatterjee, N. Prasad, Santanu Chattopadhyay:
A spare link based reliable Network-on-Chip design. 1-6 - Sumanta Pyne, Ajit Pal:
Loop unrolling with fine grained power gating for runtime leakage power reduction. 1-6 - Sreehari Rao Patri, Pavankumarsharma Devulapalli, Dhananjay Kewale, Omkar Asbe, K. S. R. Krishna Prasad:
Power optimized PLL implementation in 180nm CMOS technology. 1-2 - Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay:
Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model. 1-6 - Sanjay Singh, Ravi Saini, Sumeet Saurav, Anil K. Saini, Chandra Shekhar, Anil Vohra:
FPGA-based real-time object tracker using modified particle filtering and SAD computation. 1-2 - Shipra Bassi, Manisha Pattanaik:
TID effects on retention of 0.13 μm SONOS memory cell: A device simulation approach. 1-6 - Palash Das, Bikromadittya Mondal:
Signature analysis for synthesis of reversible circuit. 1-2 - Bhavit Kaushik, Ravi Saini, Anil K. Saini, Sanjay Singh, Atanendu S. Mandal:
An FPGA implementation of image signature based visual-saliency detection. 1-6 - Apoorv Kumar, Hemangee K. Kapoor:
Modelling and analysis of wireless communication over Networks-on-Chip. 1-6 - Kasturi Ghosh, Baidya Nath Ray:
Design of a new high order OTA-C filter structure and its specification based testing. 1-6 - Phuong Ha Nguyen, Durga Prasad Sahoo, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty:
Cryptanalysis of Composite PUFs (Extended abstract-invited talk). 1-2 - Dilsukh Nehra, Pankaj Kumar Pal, Brajesh Kumar Kaushik, S. Dasgupta:
High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications. 1-6 - Akhila Kamal, Bindu Boby:
Design of tunnel FET based low power digital circuits. 1-2 - Fradaric Joseph, Kiran Francis, Archita Hore, Siddhanta Roy, S. Josephine, Roy P. Paily:
An efficient hardware architecture for stereo disparity estimation. 1-6 - Shubhankar Majumdar, Mohd. Zuhair, Dhrubes Biswas:
Artificial neural network modelling of ADS designed Double Pole Double Throw switch. 1-2
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