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ORCIDFernando De Bernardinis
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2020 – today
- 2024
[c19]Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, T. Lovitt, Victor Karam, D. Albano, C. Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, D. Herbas, S. Ho, Enrico Monaco, Benjamín T. Reyes, P. Rossi, E. Temporiti, P. Pascale, Fernando De Bernardinis, S. Scouten, S. Jantzi:
A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process. VLSI Technology and Circuits 2024: 1-2- 2020
- [j7]Matteo Pisati
, Alberto Minuti, Giacomino Bollati, Fabio Giunco, Roberto G. Massolini, Giovanni Cesura, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Nicola Ghittori, Enrico Pozzati, Marco Sosio, Marco Garampazzi, Antonio Milani:
A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET. IEEE J. Solid State Circuits 55(1): 6-18 (2020)
2010 – 2019
- 2019
- [c18]Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti:
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET. ISSCC 2019: 116-118 - 2013
- [j6]Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Samuel Er-Shen Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello:
A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS. IEEE J. Solid State Circuits 48(11): 2746-2761 (2013) - 2012
- [j5]Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello:
A Dither-Less All Digital PLL for Cellular Transmitters. IEEE J. Solid State Circuits 47(8): 1908-1920 (2012) - [c17]Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Sam Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello:
A 40MHz-to-1GHz fully integrated multistandard silicon tuner in 80nm CMOS. ISSCC 2012: 162-164 - 2011
- [c16]Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello:
A dither-less all digital PLL for cellular transmitters. CICC 2011: 1-8 - [c15]Marco Sosio, Antonio Liscidini, Rinaldo Castello, Fernando De Bernardinis:
A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC. ESSCIRC 2011: 391-394 - 2010
- [j4]Pierluigi Nuzzo, Xuening Sun, Chang-Ching Wu, Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli:
A Platform-Based Methodology for System-Level Mixed-Signal Design. EURASIP J. Embed. Syst. 2010 (2010)
2000 – 2009
- 2008
- [j3]Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni, Geert Van der Plas:
Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1441-1454 (2008) - 2006
- [j2]Jan M. Rabaey, Fernando De Bernardinis, Ali M. Niknejad, Borivoje Nikolic, Alberto L. Sangiovanni-Vincentelli:
L. Embedding Mixed-Signal Design in Systems-on-Chip. Proc. IEEE 94(6): 1070-1088 (2006) - [c14]Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni:
A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. DAC 2006: 873-878 - [c13]Vito Giannini, Pierluigi Nuzzo, Fernando De Bernardinis, Jan Craninckx, Boris Come, Stefano D'Amico, Andrea Baschirotto:
A synthesis tool for power-efficient base-band filter design. DATE 2006: 162-163 - [c12]Fernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli:
Robust system level design with analog platforms. ICCAD 2006: 334-341 - 2005
- [c11]Yanmei Li, Fernando De Bernardinis, Brian P. Otis, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
A low-power mixed-signal baseband system design for wireless sensor networks. CICC 2005: 55-58 - [c10]Fernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli:
Mixed signal design space exploration through analog platforms. DAC 2005: 875-880 - [c9]Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli:
Efficient analog platform characterization through analog constraint graphs. ICCAD 2005: 415-421 - [c8]Fernando De Bernardinis, Pierluigi Nuzzo, Pierangelo Terreni, Alberto L. Sangiovanni-Vincentelli:
Enriching an analog platform for analog-to-digital converter design. ISCAS (2) 2005: 1286-1289 - [p1]Luca P. Carloni, Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi:
Platform-Based and Derivative Design. The Industrial Information Technology Handbook 2005: 1-15 - [r1]Marco Sgroi, Alberto L. Sangiovanni-Vincentelli, Fernando De Bernardinis, Claudio Pinello, Luca P. Carloni:
Platform-Based Design for Embedded Systems. Embedded Systems Handbook 2005 - 2004
- [c7]Alberto L. Sangiovanni-Vincentelli, Luca P. Carloni, Fernando De Bernardinis, Marco Sgroi:
Benefits and challenges for platform-based design. DAC 2004: 409-414 - [c6]Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli:
A Methodology for System-Level Analog Design Space Exploration. DATE 2004: 676-677 - 2003
- [c5]Fernando De Bernardinis, Michael I. Jordan, Alberto L. Sangiovanni-Vincentelli:
Support vector machines for analog circuit performance representation. DAC 2003: 964-969 - [c4]Fernando De Bernardinis, Luca Fanucci, Tommaso Ramacciotti, Pierangelo Terreni:
A QoS Internet Protocol Scheduler on the IXP1200 Network Platform. IWSOC 2003: 394-399 - 2000
- [c3]Julio Leao da Silva Jr., Marco Sgroi, Fernando De Bernardinis, Suet-Fei Li, Alberto L. Sangiovanni-Vincentelli, Jan M. Rabaey:
Wireless protocols design: challenges and opportunities. CODES 2000: 147-151 - [c2]Marco Sgroi, Julio Leao da Silva Jr., Fernando De Bernardinis, Fred L. Burghardt, Alberto L. Sangiovanni-Vincentelli, Jan M. Rabaey:
Designing wireless protocols: methodology and applications. ICASSP 2000: 3726-3729
1990 – 1999
- 1999
- [j1]Fernando De Bernardinis, Roberto Roncella, Roberto Saletti, Pierangelo Terreni, Graziano Bertini:
An efficient VLSI architecture for real-time additive synthesis of musical signals. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 105-110 (1999) - 1997
- [c1]Fernando De Bernardinis, Roberto Roncella, Roberto Saletti, Pierangelo Terreni, Graziano Bertini:
A single-chip 1, 200 sinusoid real-time generator for additive synthesis of musical signals. ICASSP 1997: 427-430
Coauthor Index
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