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ORCIDMehran Goli
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2020 – today
- 2024
[j5]Mehran Goli
, Rolf Drechsler:
Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL. ACM Trans. Embed. Comput. Syst. 23(5): 67:1-67:20 (2024)- 2023
- [c32]Rune Krauss, Mehran Goli, Rolf Drechsler:
EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation. ASP-DAC 2023: 423-428 - [c31]Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler:
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. ASP-DAC 2023: 683-689 - [c30]Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler:
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. DATE 2023: 1-2 - [c29]Rune Krauss, Mehran Goli, Rolf Drechsler:
Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes. DDECS 2023: 73-78 - [c28]Weiyan Zhang, Mehran Goli, Muhammad Hassan, Rolf Drechsler:
Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors. DSD 2023: 693-699 - [c27]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs. IPDPS Workshops 2023: 754-760 - [c26]Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, Rolf Drechsler:
VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking. ISQED 2023: 1-8 - [c25]Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler:
Polynomial Formal Verification of a Processor: A RISC-V Case Study. ISQED 2023: 1-7 - [c24]Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler:
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing. ISVLSI 2023: 1-6 - 2022
- [j4]Mehran Goli, Rolf Drechsler:
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1181-1185 (2022) - [c23]Rolf Drechsler, Alireza Mahzoon, Mehran Goli:
Towards Polynomial Formal Verification of Complex Arithmetic Circuits. DDECS 2022: 1-6 - [c22]Weiyan Zhang, Mehran Goli, Rolf Drechsler:
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression. DDECS 2022: 20-25 - [c21]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
ML-based Power Estimation of Convolutional Neural Networks on GPGPUs. DDECS 2022: 166-171 - [c20]Mehran Goli, Rolf Drechsler:
Simulation-based Verification of SystemC-based VPs at the ESL. MBMV 2022: 1-4 - [c19]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling. MLCAD 2022: 103-109 - [c18]Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler:
ANN-based Performance Estimation of Embedded Software for RISC-V Processors. RSP 2022: 22-28 - [i2]Mehran Goli, Rolf Drechsler:
Simulation-based Verification of SystemC-based VPs at the ESL. CoRR abs/2202.08046 (2022) - 2021
- [c17]Mehran Goli, Rolf Drechsler:
ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs. ASP-DAC 2021: 67-72 - [c16]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Early power estimation of CUDA-based CNNs on GPGPUs: work-in-progress. CODES+ISSS 2021: 29-30 - [c15]Mehran Goli, Alireza Mahzoon, Rolf Drechsler:
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs. DSD 2021: 519-526 - [c14]Mehran Goli, Rolf Drechsler:
VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes. FDL 2021: 1-8 - [c13]Mehran Goli, Rolf Drechsler:
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs. ICCAD 2021: 1-8 - [i1]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs. CoRR abs/2102.02645 (2021) - 2020
- [j3]Mehran Goli, Jannis Stoppe, Rolf Drechsler:
Automated Nonintrusive Analysis of Electronic System Level Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 492-505 (2020) - [j2]Mehran Goli, Rolf Drechsler:
PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques. ACM Trans. Design Autom. Electr. Syst. 25(5): 40:1-40:28 (2020) - [c12]David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler:
Towards Generation of a Programmable Power Management Unit at the Electronic System Level. DDECS 2020: 1-6 - [c11]Mehran Goli, Alireza Mahzoon, Rolf Drechsler:
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique. ICCD 2020: 179-186 - [c10]Mehran Goli, Rolf Drechsler:
Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization. ISVLSI 2020: 188-193
2010 – 2019
- 2019
- [j1]Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler:
Security validation of VP-based SoCs using dynamic information flow tracking. it Inf. Technol. 61(1): 45-58 (2019) - [c9]Mehran Goli, Rolf Drechsler:
Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes. DSD 2019: 522-529 - [c8]Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler:
Automated Analysis of Virtual Prototypes at Electronic System Level. ACM Great Lakes Symposium on VLSI 2019: 307-310 - [p1]Mehran Goli:
Automatisierte Analyse virtueller Prototypen auf der ESL. Ausgezeichnete Informatikdissertationen 2019: 89-98 - 2018
- [c7]David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler:
Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters*. NORCAS 2018: 1-6 - [c6]Mehran Goli, Jannis Stoppe, Rolf Drechsler:
Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques. RSP 2018: 97-103 - 2017
- [c5]Mehran Goli, Jannis Stoppe, Rolf Drechsler:
Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications. DATE 2017: 630-633 - [c4]Mehran Goli, Jannis Stoppe, Rolf Drechsler:
Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata. ICCD 2017: 377-384 - 2016
- [c3]Mehran Goli, Jannis Stoppe, Rolf Drechsler:
AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration. ICCD 2016: 360-363 - 2015
- [c2]Mehran Goli, Amin Ghasemazar, Zainalabedin Navabi:
Application-specific power-aware mapping for reconfigurable NoC architectures. DTIS 2015: 1-6 - 2014
- [c1]Amin Ghasemazar, Mehran Goli, Ali Afzali-Kusha:
Embedded Complex Floating Point Hardware Accelerator. VLSID 2014: 318-323
Coauthor Index
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last updated on 2024-10-04 20:00 CEST by the dblp team
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