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Daniel Große
Person information
- affiliation: JKU Linz, Austria
- affiliation (former): University of Bremen, Germany
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2020 – today
- 2025
- [j24]Christoph Hazott
, Florian Stögmüller, Daniel Große
:
Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries. Integr. 101: 102320 (2025) - 2024
- [j23]Lucas Klemmer
, Daniel Große
:
WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3198-3211 (2024) - [j22]Julien Deantoni
, Alain Girault
, Daniel Große
:
Introduction to the Special Issue on Specification and Design Languages (FDL 2021). ACM Trans. Embed. Comput. Syst. 23(5): 65:1-65:4 (2024) - [c168]Christoph Hazott, Florian Stögmüller, Daniel Große:
Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing. ASPDAC 2024: 275-281 - [c167]Lucas Klemmer
, Daniel Große:
Towards a Highly Interactive Design-Debug-Verification Cycle. ASPDAC 2024: 692-697 - [c166]Daniel Große, Lucas Klemmer, Dominik Bonora:
Using Formal Verification Methods for Optimization of Circuits Under External Constraints. DATE 2024: 1-6 - [c165]Manfred Schlägl
, Moritz Stockinger, Daniel Große:
A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level. DATE 2024: 1-6 - [c164]Christoph Hazott, Daniel Große:
Relation Coverage: A New Paradigm for Hardware/Software Testing. ETS 2024: 1-4 - [c163]Lucas Klemmer, Daniel Große:
An Extensible and Flexible Methodology for Analyzing the Cache Performance of Hardware Designs. FDL 2024: 1-8 - 2023
- [c162]Katharina Ruep, Daniel Große:
Improving Design Understanding of Processors leveraging Datapath Clustering. DATE 2023: 1-2 - [c161]Frans Skarman, Lucas Klemmer
, Oscar Gustafsson, Daniel Große:
Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis. FDL 2023: 1-8 - [c160]Manfred Schlägl
, Daniel Große
:
GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development. ACM Great Lakes Symposium on VLSI 2023: 599-605 - [i3]Lucas Klemmer, Daniel Große:
Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV. CoRR abs/2304.05837 (2023) - 2022
- [j21]Alireza Mahzoon
, Daniel Große
, Rolf Drechsler
:
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1573-1586 (2022) - [c159]Lucas Klemmer
, Daniel Große:
WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging. ASP-DAC 2022: 358-364 - [c158]Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
:
Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. DAC 2022: 1177-1182 - [c157]Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
:
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. DAC 2022: 1183-1188 - [c156]Lucas Klemmer
, Daniel Große:
Waveform-based performance analysis of RISC-V processors: late breaking results. DAC 2022: 1404-1405 - [c155]Katharina Ruep, Daniel Große:
SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs. ETS 2022: 1-4 - [c154]Lucas Klemmer
, Sonja Gurtner, Daniel Große:
Formal Verification of SUBLEQ Microcode implementing the RV32I ISA. FDL 2022: 1-8 - [c153]Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler:
Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. FMCAD 2022: 1-10 - [c152]Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
:
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. ACM Great Lakes Symposium on VLSI 2022: 97-103 - [c151]Lucas Klemmer
, Manfred Schlägl
, Daniel Große:
RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V. ACM Great Lakes Symposium on VLSI 2022: 183-187 - [c150]Lucas Klemmer
, Daniel Große:
An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle. ISVLSI 2022: 38-43 - 2021
- [j20]Niklas Bruns
, Vladimir Herdt, Daniel Große
, Rolf Drechsler
:
Toward RISC-V CSR Compliance Testing. IEEE Embed. Syst. Lett. 13(4): 202-205 (2021) - [j19]Vladimir Herdt
, Daniel Große, Sören Tempel, Rolf Drechsler
:
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. 116: 102135 (2021) - [c149]Vladimir Herdt, Sören Tempel
, Daniel Große, Rolf Drechsler
:
Mutation-based Compliance Testing for RISC-V. ASP-DAC 2021: 55-60 - [c148]Muhammad Hassan, Daniel Große, Rolf Drechsler
:
System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. ASP-DAC 2021: 761-766 - [c147]Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler
:
Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. DATE 2021: 1110-1115 - [c146]Muhammad Hassan, Daniel Große, Rolf Drechsler
:
System Level Verification of Phase-Locked Loop using Metamorphic Relations. DATE 2021: 1378-1381 - [c145]Lucas Klemmer
, Daniel Große:
EPEX: Processor Verification by Equivalent Program Execution. ACM Great Lakes Symposium on VLSI 2021: 33-38 - [c144]Lucas Klemmer
, Saman Fröhlich, Rolf Drechsler
, Daniel Große:
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding. ISCAS 2021: 1-5 - [c143]Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler
:
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. VLSI-SoC 2021: 1-6 - 2020
- [j18]Vladimir Herdt
, Daniel Große, Pascal Pieper
, Rolf Drechsler
:
RISC-V based virtual prototype: An extensible and configurable platform for the system-level. J. Syst. Archit. 109: 101756 (2020) - [j17]Frank Sill Torres, Pedro Arthur Silva, Geraldo Fontes, Marcel Walter
, José Augusto Miranda Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto
, Jeferson F. Chaves
, Robert Wille, Philipp Niemann, Daniel Große, Rolf Drechsler
:
On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata. Microprocess. Microsystems 76: 103109 (2020) - [c142]Vladimir Herdt
, Daniel Große
, Rolf Drechsler
:
RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. ATVA 2020: 543-549 - [c141]Vladimir Herdt, Daniel Große, Rolf Drechsler
:
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side*. DAC 2020: 1-6 - [c140]Pascal Pieper
, Vladimir Herdt, Daniel Große, Rolf Drechsler
:
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. DAC 2020: 1-6 - [c139]Marcel Walter
, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
:
Verification for Field-coupled Nanocomputing Circuits. DAC 2020: 1-6 - [c138]Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
:
Towards Formal Verification of Optimized and Industrial Multipliers. DATE 2020: 544-549 - [c137]Vladimir Herdt, Daniel Große, Rolf Drechsler
:
Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes*. DATE 2020: 618-621 - [c136]Vladimir Herdt, Daniel Große, Rolf Drechsler
:
Towards Specification and Testing of RISC-V ISA Compliance⋆. DATE 2020: 995-998 - [c135]David Lemma, Mehran Goli
, Daniel Große, Rolf Drechsler
:
Towards Generation of a Programmable Power Management Unit at the Electronic System Level. DDECS 2020: 1-6 - [c134]Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler
:
Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. FDL 2020: 1-7 - [c133]Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler
:
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes. ACM Great Lakes Symposium on VLSI 2020: 101-106 - [c132]Niklas Bruns, Daniel Große, Rolf Drechsler
:
Early Verification of ISA Extension Specifications using Deep Reinforcement Learning. ACM Great Lakes Symposium on VLSI 2020: 297-302 - [c131]Vladimir Herdt, Daniel Große, Sören Tempel
, Rolf Drechsler
:
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. ICCD 2020: 312-315 - [c130]Tim Meywerk
, Marcel Walter
, Daniel Große
, Rolf Drechsler
:
Clustering-Guided SMT($\mathcal {L\!R\!A}$) Learning. IFM 2020: 41-59 - [c129]Saman Fröhlich, Lucas Klemmer
, Daniel Große, Rolf Drechsler
:
ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks. ISMVL 2020: 64-69 - [c128]Tim Meywerk
, Marcel Walter
, Vladimir Herdt
, Jan Kleinekathöfer
, Daniel Große
, Rolf Drechsler
:
Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. ISoLA (3) 2020: 326-347
2010 – 2019
- 2019
- [j16]Mehran Goli
, Muhammad Hassan, Daniel Große
, Rolf Drechsler
:
Security validation of VP-based SoCs using dynamic information flow tracking. it Inf. Technol. 61(1): 45-58 (2019) - [j15]Marcel Walter
, Robert Wille, Daniel Große
, Frank Sill Torres
, Rolf Drechsler
:
Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is NP-complete (Research Note). ACM J. Emerg. Technol. Comput. Syst. 15(3): 29:1-29:10 (2019) - [j14]Vladimir Herdt, Hoang M. Le, Daniel Große
, Rolf Drechsler
:
Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction. Int. J. Softw. Tools Technol. Transf. 21(5): 545-565 (2019) - [j13]Vladimir Herdt
, Hoang M. Le
, Daniel Große
, Rolf Drechsler
:
Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1359-1372 (2019) - [c127]Kenneth Schmitz
, Buse Ustaoglu
, Daniel Große
, Rolf Drechsler
:
(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs. ARC 2019: 112-126 - [c126]Marcel Walter
, Robert Wille, Frank Sill Torres
, Daniel Große
, Rolf Drechsler
:
Scalable design for field-coupled nanocomputing circuits. ASP-DAC 2019: 197-202 - [c125]Vladimir Herdt, Hoang M. Le, Daniel Große
, Rolf Drechsler
:
Maximizing power state cross coverage in firmware-based power management. ASP-DAC 2019: 335-340 - [c124]Rolf Drechsler, Daniel Große:
Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems. ATS 2019: 159-164 - [c123]Alireza Mahzoon, Daniel Große
, Rolf Drechsler
:
RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. DAC 2019: 185 - [c122]Vladimir Herdt, Daniel Große
, Hoang M. Le, Rolf Drechsler
:
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. DAC 2019: 188 - [c121]Saman Fröhlich, Daniel Große
, Rolf Drechsler
:
One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing. DATE 2019: 284-287 - [c120]Vladimir Herdt, Daniel Große
, Hoang M. Le, Rolf Drechsler
:
Verifying Instruction Set Simulators using Coverage-guided Fuzzing*. DATE 2019: 360-365 - [c119]Muhammad Hassan, Daniel Große
, Hoang M. Le, Rolf Drechsler
:
Data Flow Testing for SystemC-AMS Timed Data Flow Models. DATE 2019: 366-371 - [c118]Hoang M. Le, Daniel Große
, Niklas Bruns, Rolf Drechsler
:
Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing. DATE 2019: 602-605 - [c117]Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres
, Daniel Große
, Rolf Drechsler
:
SAT-Hard: A Learning-Based Hardware SAT-Solver. DSD 2019: 74-81 - [c116]Tim Meywerk, Marcel Walter
, Vladimir Herdt, Daniel Große
, Rolf Drechsler
:
Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. DSD 2019: 129-136 - [c115]Muhammad Hassan, Daniel Große
, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
:
Functional Coverage-Driven Characterization of RF Amplifiers. FDL 2019: 1-8 - [c114]Vladimir Herdt, Daniel Große
, Rolf Drechsler
, Christoph Gerum, Alexander Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz:
Systematic RISC-V based Firmware Design⋆. FDL 2019: 1-8 - [c113]Mehran Goli
, Muhammad Hassan, Daniel Große
, Rolf Drechsler
:
Automated Analysis of Virtual Prototypes at Electronic System Level. ACM Great Lakes Symposium on VLSI 2019: 307-310 - [c112]Robert Wille, Marcel Walter
, Frank Sill Torres
, Daniel Große
, Rolf Drechsler
:
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies. ISVLSI 2019: 651-656 - [p2]Saman Fröhlich, Daniel Große
, Rolf Drechsler:
Approximate Hardware Generation Using Formal Techniques. Approximate Circuits 2019: 155-174 - [e2]Daniel Große, Sara Vinco, Hiren D. Patel:
Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 [Verona, Italy, September 18-20, 2017]. Lecture Notes in Electrical Engineering 530, Springer 2019, ISBN 978-3-030-02214-3 [contents] - [i2]Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler:
fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits. CoRR abs/1905.02477 (2019) - 2018
- [j12]Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große
, Rolf Drechsler
:
Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. 11: 29-45 (2018) - [c111]Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große
, Rolf Drechsler
:
Approximation-aware testing for approximate circuits. ASP-DAC 2018: 239-244 - [c110]Marcel Walter
, Robert Wille, Daniel Große
, Frank Sill Torres
, Rolf Drechsler
:
An exact method for design exploration of quantum-dot cellular automata. DATE 2018: 503-508 - [c109]Hoang M. Le, Vladimir Herdt, Daniel Große
, Rolf Drechsler
:
Resilience evaluation via symbolic fault injection on intermediate code. DATE 2018: 845-850 - [c108]Muhammad Hassan, Daniel Große
, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
:
Testbench qualification for SystemC-AMS timed data flow models. DATE 2018: 857-860 - [c107]Saman Fröhlich, Daniel Große
, Rolf Drechsler
:
Approximate hardware generation using symbolic computer algebra employing grobner basis. DATE 2018: 889-892 - [c106]Vladimir Herdt, Hoang M. Le, Daniel Große
, Rolf Drechsler
:
Towards fully automated TLM-to-RTL property refinement. DATE 2018: 1508-1511 - [c105]David Lemma, Daniel Große
, Rolf Drechsler
:
Natural Language Based Power Domain Partitioning. DDECS 2018: 101-106 - [c104]Frank Sill Torres
, Robert Wille, Marcel Walter
, Philipp Niemann, Daniel Große
, Rolf Drechsler
:
Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata. DSD 2018: 649-656 - [c103]Saman Fröhlich, Daniel Große
, Rolf Drechsler
:
Towards Reversed Approximate Hardware Design. DSD 2018: 665-671 - [c102]Vladimir Herdt, Daniel Große
, Hoang M. Le, Rolf Drechsler
:
Extensible and Configurable RISC-V Based Virtual Prototype. FDL 2018: 5-16 - [c101]Buse Ustaoglu, Sebastian Huhn, Daniel Große
, Rolf Drechsler
:
SAT-Lancer: A Hardware SAT-Solver for Self-Verification. ACM Great Lakes Symposium on VLSI 2018: 479-482 - [c100]Alireza Mahzoon, Daniel Große
, Rolf Drechsler
:
PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. ICCAD 2018: 129 - [c99]Alireza Mahzoon, Daniel Große
, Rolf Drechsler
:
Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. ISVLSI 2018: 351-356 - [c98]Kenneth Schmitz, Oliver Keszöcze
, Jurij Schmidt, Daniel Große
, Rolf Drechsler
:
Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws. ISVLSI 2018: 557-562 - [c97]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards Automated Refinement of TLM Properties to RTL. MBMV 2018 - [c96]David Lemma, Mehran Goli
, Daniel Große
, Rolf Drechsler
:
Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters*. NORCAS 2018: 1-6 - 2017
- [j11]Heinz Riener
, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große
, Rolf Drechsler
, Görschwin Fey
:
metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. 19(5): 605-621 (2017) - [c95]Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große
, Rolf Drechsler
:
Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. ASP-DAC 2017: 57-62 - [c94]Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große
, Rolf Drechsler
:
Data flow testing for virtual prototypes. DATE 2017: 380-385 - [c93]Vladimir Herdt, Hoang M. Le, Daniel Große
, Rolf Drechsler
:
Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. FDL 2017: 1-8 - [c92]Vladimir Herdt, Hoang M. Le, Daniel Große
, Rolf Drechsler
:
Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. FDL (Selected Papers) 2017: 25-44 - [c91]Rehab Massoud
, Jannis Stoppe
, Daniel Große
, Rolf Drechsler
:
Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction. FORMATS 2017: 335-351 - [c90]Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
:
An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization. GECCO 2017: 1232-1239 - [c89]Arun Chandrasekharan, Daniel Große
, Rolf Drechsler
:
ProACt: A Processor for High Performance On-demand Approximate Computing. ACM Great Lakes Symposium on VLSI 2017: 463-466 - [c88]Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große
, Rolf Drechsler
:
Early SoC security validation by VP-based static information flow analysis. ICCAD 2017: 400-407 - [c87]Saman Fröhlich, Daniel Große, Rolf Drechsler
:
Error Bounded Exact BDD Minimization in Approximate Computing. ISMVL 2017: 254-259 - [c86]Saman Fröhlich, Daniel Große, Rolf Drechsler:
Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing. MBMV 2017: 27-38 - [c85]Arun Chandrasekharan, Daniel Große
, Rolf Drechsler
:
Yise - a novel framework for boolean networks using y-inverter graphs. MEMOCODE 2017: 114-117 - [e1]Daniel Große, Rolf Drechsler:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017. Shaker Verlag 2017, ISBN 978-3-8440-4996-1 [contents] - 2016
- [c84]Mathias Soeken, Daniel Große
, Arun Chandrasekharan, Rolf Drechsler
:
BDD minimization for approximate computing. ASP-DAC 2016: 474-479 - [c83]Vladimir Herdt, Hoang Minh Le, Daniel Große
, Rolf Drechsler
:
ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. CAV (2) 2016: 177-183 - [c82]Arun Chandrasekharan, Mathias Soeken, Daniel Große
, Rolf Drechsler
:
Precise error determination of approximated components in sequential circuits with model checking. DAC 2016: 129:1-129:6 - [c81]Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler:
Quantitative timing analysis of UML activity diagrams using statistical model checking. DATE 2016: 780-785 - [c80]Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler:
Formal verification of integer multipliers by combining Gröbner basis with logic reduction. DATE 2016: 1048-1053 - [c79]Hoang Minh Le, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Towards formal verification of real-world SystemC TLM peripheral models - a case study. DATE 2016: 1160-1163 - [c78]Vladimir Herdt, Hoang M. Le, Daniel Große
, Rolf Drechsler
:
On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. FDL 2016: 1-8 - [c77]Amr A. R. Sayed-Ahmed, Daniel Große
, Mathias Soeken, Rolf Drechsler
:
Equivalence checking using Gröbner bases. FMCAD 2016: 169-176 - [c76]Saeideh Shirinzadeh, Mathias Soeken, Daniel Große
, Rolf Drechsler
:
Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. GECCO (Companion) 2016: 79-80 - [c75]Vladimir Herdt, Hoang M. Le, Daniel Große
, Rolf Drechsler
:
Compiled symbolic simulation for systemC. ICCAD 2016: 52 - [c74]Arun Chandrasekharan, Mathias Soeken, Daniel Große
, Rolf Drechsler
:
Approximation-aware rewriting of AIGs for error tolerant applications. ICCAD 2016: 83 - [c73]Daniel Große
, Hoang M. Le, Muhammad Hassan, Rolf Drechsler
:
Guided lightweight Software test qualification for IP integration using Virtual Prototypes. ICCD 2016: 606-613 - [c72]