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2020 – today
- 2025
[i6]Aman Kumar, Deepak Narayan Gadde, Keerthan Kopparam Radhakrishna, Djones Lettnin:
Saarthi: The First AI Formal Verification Engineer. CoRR abs/2502.16662 (2025)- 2024
- [c28]Deepak Narayan Gadde, Thomas Nalapat, Aman Kumar, Djones Lettnin, Wolfgang Kunz, Sebastian Simon:
Efficient Stimuli Generation using Reinforcement Learning in Design Verification. SMACD 2024: 1-4 - [c27]Paulette Iskandar, Bryan Olmos, Wolfgang Kunz, Djones Lettnin:
Adaptable FWHW Formal Co-Verification of SoC RISC-V Components. VLSI-SoC 2024: 1-6 - [c26]Jaimini Nagar, Thorsten Dworzak, Sebastian Simon, Ulrich Heinkel, Djones Lettnin:
Exploring the Role of the Portable Stimulus Standard in Enhancing Security Property Verification. VLSI-SoC 2024: 1-4 - [i5]Deepak Narayan Gadde, Sebastian Simon, Djones Lettnin, Thomas Ziller:
Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification. CoRR abs/2405.17481 (2024) - [i4]Deepak Narayan Gadde, Thomas Nalapat, Aman Kumar, Djones Lettnin, Wolfgang Kunz, Sebastian Simon:
Efficient Stimuli Generation using Reinforcement Learning in Design Verification. CoRR abs/2405.19815 (2024) - [i3]Deepak Narayan Gadde, Aman Kumar, Djones Lettnin, Sebastian Simon:
FuzzWiz - Fuzzing Framework for Efficient Hardware Coverage. CoRR abs/2410.17732 (2024) - [i2]Bryan Olmos, Daniel Gerl, Aman Kumar, Djones Lettnin:
Verifying Non-friendly Formal Verification Designs: Can We Start Earlier? CoRR abs/2410.18454 (2024)
2010 – 2019
- 2018
- [c25]Douglas Lohmann, Alexis Huf
, Djones Lettnin, Frank Siqueira, José Luís Güntzel:
A Domain-specific Language for Automated Fault Injection in SystemC Models. ICECS 2018: 425-428 - [c24]Tomás Grimm, Djones Lettnin, Michael Hübner:
ARCHVerifyr: An Embedded Software-Driven Approach for Architecture Verification. ISVLSI 2018: 220-225 - [c23]Douglas Lohmann, Fabrizio Maziero, Elço João dos Santos Jr, Djones Lettnin:
Extending universal verification methodology with fault injection capabilities. LASCAS 2018: 1-4 - [c22]Jeferson Santos Barros, Victor Hugo Schulz, Djones Vinicius Lettnin:
An Adaptive Closed-Loop Verification Approach in UVM-SystemC for AMS Circuits. SBCCI 2018: 1-6 - [i1]Tomás Grimm, Djones Lettnin, Michael Hübner:
A Scalable Approach for Hardware Semiformal Verification. CoRR abs/1801.08446 (2018) - 2017
- [c21]Tomás Grimm, Djones Lettnin, Michael Hübner:
Semiformal Verification of Software-Controlled Connections. ISVLSI 2017: 556-561 - 2016
- [c20]Rogerio Paludo, Djones Lettnin:
A methodology for early functional verification of embedded software combining virtual platforms and bounded model checking. LATS 2016: 141-146 - [c19]Tomás Grimm, Djones Lettnin, Michael Hübner:
Automatic generation of RTL connectivity checkers from SystemC TLM and IP-XACT descriptions. NORCAS 2016: 1-6 - 2015
- [j1]Jörg Behrend, Djones Lettnin, Alexander Grünhage, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
Scalable and Optimized Hybrid Verification of Embedded Software. J. Electron. Test. 31(2): 151-166 (2015) - [c18]Paulo Ricardo Cechelero Villa, Eduardo Augusto Bezerra, Djones Vinicius Lettnin, Samir Ahmad Mussa:
A reconfigurable hardware platform for power converter control systems. ICIT 2015: 1560-1563 - 2014
- [c17]Jörg Behrend, Alexander Grünhage, Douglas Schroeder, Djones Lettnin, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
Optimized hybrid verification of embedded software. LATW 2014: 1-6 - [c16]Victor M. Goncalves Martins, Frederico Ferlini, Djones Vinicius Lettnin, Eduardo Augusto Bezerra:
Low cost fault detector guided by permanent faults at the end of FPGAs life cycle. LATW 2014: 1-6 - 2013
- [c15]Wesley Silva, Eduardo Augusto Bezerra, Markus Winterholer, Djones Lettnin:
Automatic property generation for formal verification applied to HDL-based design of an on-board computer for space applications. LATW 2013: 1-6 - 2012
- [c14]Frederico Ferlini, Felipe A. da Silva, Eduardo Augusto Bezerra, Djones Vinicius Lettnin:
Non-intrusive fault tolerance in soft processors through circuit duplication. LATW 2012: 1-6 - [c13]Alexander Grünhage, Jörg Behrend, Patrick Heckeler, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Djones Lettnin:
Optimized Static Parameter Assignment for Semiformal Software Verification. MBMV 2012: 25-35 - 2011
- [c12]Jörg Behrend, Djones Lettnin, Patrick Heckeler, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
Scalable hybrid verification for embedded software. DATE 2011: 179-184 - [c11]Djones Lettnin, Wolfgang Rosenstiel:
Hybrid verificatio of temporal properties in hardware dependent software. LATW 2011: 1-6 - [c10]Jörg Behrend, Patrick Heckeler, Stefan Huster, Djones Lettnin, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
Scalable and Extendable Hybrid Verification Platform. MBMV 2011: 259-268 - 2010
- [c9]Andreas Braun, Oliver Bringmann, Djones Lettnin, Wolfgang Rosenstiel:
Simulation-based verification of the MOST NetInterface specification revision 3.0. DATE 2010: 538-543
2000 – 2009
- 2009
- [b1]Djones Vinicius Lettnin:
Verification of temporal properties in embedded software. University of Tübingen, Germany, 2009, pp. 1-134 - [c8]Djones Lettnin, Pradeep Kumar Nalla, Jörg Behrend, Jürgen Ruf, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Volker Schönknecht, Stephan Reitemeyer:
Semiformal verification of temporal properties in automotive hardware dependent software. DATE 2009: 1214-1217 - 2008
- [c7]Djones Lettnin, Pradeep Kumar Nalla, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Tobias Kirsten, Volker Schönknecht, Stephan Reitemeyer:
Verification of Temporal Properties in Automotive Embedded Software. DATE 2008: 164-169 - 2007
- [c6]Djones Lettnin, Markus Winterholer, Axel G. Braun, Joachim Gerlach, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
Coverage Driven Verification applied to Embedded Software. ISVLSI 2007: 159-164 - [c5]Djones Lettnin, Pradeep Kumar Nalla, Jürgen Ruf, Roland J. Weiss, Axel G. Braun, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel:
Semiformal Verification of Temporal Properties in Embedded Software. MBMV 2007: 19-28 - 2004
- [c4]Djones Lettnin, Axel G. Braun, Martin Bogdan, Joachim Gerlach, Wolfgang Rosenstiel:
Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks. DATE 2004: 248-255 - 2003
- [c3]Axel G. Braun, Djones Lettnin, Joachim Gerlach, Wolfgang Rosenstiel:
Automated Conversion of SystemC Fixed-Point Data Types. VLSI-SoC (Selected Papers) 2003: 55-72 - 2002
- [c2]Fabian Vargas, Djones Lettnin, Diogo B. Brum, Dárcio Prestes:
A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead. Asian Test Symposium 2002: 218-223 - [c1]Fabian Vargas, Maria Cristina Felippetto de Castro, Marcello Macarthy, Djones Lettnin:
Electrocardiogram Pattern Recognition by Means of MLP Network and PCA: A Case Study on Equal Amount of Input Signal Types. SBRN 2002: 200-205
Coauthor Index
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