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ORCIDLATW 2013: Cordoba, Argentina
- 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013. IEEE Computer Society 2013, ISBN 978-1-4799-0595-9
Keynote Address
- Raimund Ubar
:
Diagnostic modeling of digital systems with low- and high-level decision diagrams. 1
Session 1: Simulation, Diagnosis and Variability
- Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Jie Jiang, Ilia Polian, Bernd Becker:
Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. 1-6 - Shyam Kumar Devarakond, Jennifer McCoy, Amit Nahar, John M. Carulli Jr., Soumendu Bhattacharya, Abhijit Chatterjee:
Predicting die-level process variations from wafer test data for analog devices: A feasibility study. 1-6
Session 2: Software, Hardware and Architecture Fault-Tolerance
- Eduardo Chielle, José Rodrigo Azambuja, Raul S. Barth, Fernanda Lima Kastensmidt:
Improving error detection with selective redundancy in software-based techniques. 1-6 - Martin Kohlík, Hana Kubátová:
Markov chains hierarchical dependability models: Worst-case computations. 1-6 - Arwa Ben Dhia, Lirida A. B. Naviner, Philippe Matherat:
Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs. 1-6
Invited Talk
- Sybille Hellebrand:
Analyzing and quantifying fault tolerance properties. 1
Session 3: Design Verification and Validation (Part I)
- Wesley Silva, Eduardo Augusto Bezerra, Markus Winterholer, Djones Lettnin:
Automatic property generation for formal verification applied to HDL-based design of an on-board computer for space applications. 1-6 - Joel Ivan Munoz Quispe, Marius Strum, Jiang Chau Wang:
PrOCov: Probabilistic output coverage model. 1-6 - Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
Assessment of diagnostic test for automated bug localization. 1-6
Session 4: Design Verification and Validation (Part II)
- Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang:
Formal equivalence checking between high-level and RTL hardware designs. 1-6 - Guilherme Freire Roberto, Kalinka R. L. J. Castelo Branco, José Marcio Machado, Alex R. Pinto:
Local data fusion algorithm for fire detection through mobile robot. 1-6 - Pablo A. Petrashin, Carlos Dualibe, Walter J. Lancioni, Luis E. Toledo:
Low-cost DC BIST for analog circuits: A case study. 1-4 - Luis Francisco, Manuel Jiménez:
Parametric model calibration and measurement extraction for LFN using virtual instrumentation. 1-6
Session 5: Analog Mixed Signal Test
- Debesh Bhatta, Aritra Banerjee, Sabyasachi Deyati, Nicholas Tzou, Abhijit Chatterjee:
Low cost signal reconstruction based testing of RF components using incoherent undersampling. 1-5 - Hector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastià A. Bota, Jaime Martínez-Castillo, Jaume Segura:
Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. 1-6
Special Session: Emerging Technologies and Beyond CMOS Computing Architectures
- Alon Ascoli, Ronald Tetzlaff, Fernando Corinto, Miroslav Mirchev, Marco Gilli:
Memristor-based filtering applications. 1-6 - Pierre-Emmanuel Gaillardon, Hassan Ghasemzadeh, Giovanni De Micheli:
Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. 1-6 - Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino, Letícia Maria Veiras Bolzani Poehls:
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. 1-6
Invited Talk
- Rolf Drechsler, Melanie Diepenbeck, Stephan Eggersglüß, Robert Wille:
PASSAT 2.0: A multi-functional SAT-based testing framework. 1
Session 6: Software and Hardware Testing
- Mario Schölzel, Tobias Koal, Stephanie Roder, Heinrich Theodor Vierhaus:
Towards an automatic generation of diagnostic in-field SBST for processor components. 1-6 - D. Changdao, Mariagrazia Graziano, Ernesto Sánchez, Matteo Sonza Reorda, Maurizio Zamboni, N. Zhifan:
On the functional test of the BTB logic in pipelined and superscalar processors. 1-6 - Jorge H. Meza Escobar, Jörg Sachße, Steffen Ostendorff, Heinz-Dietrich Wuttke:
ISA configurability of an FPGA test-processor used for board-level interconnection testing. 1-6 - Ozgur Sinanoglu:
Embedded tutorial: Regaining hardware security and trust. 1
Invited Talk
- Luis Entrena:
Fast fault injection techniques using FPGAs. 1
Session 7: Radiation and Electromagnetic Interference
- Alexandre Boyer, Sonia Ben Dhia:
Effect of aging on power integrity of digital integrated circuits. 1-5 - Santiago Martin Sondón, Alfredo Falcon, Pablo Sergio Mandolesi, Pedro Julián, Nahuel Vega, Francisco Nesprias, Jorge Davidson, Felix Palumbo, Mario Debray:
Diagnose of radiation induced single event effects in a PLL using a heavy ion microbeam. 1-5 - Paolo Rech, Caroline Aguiar, Christopher Frost, Luigi Carro:
Neutron sensitivity of integer and floating point operations executed in GPUs. 1-6 - Karine Castellani-Coulié, Marc Bocquet, Hassen Aziza, Jean-Michel Portal, Wenceslas Rahajandraibe, Christophe Muller:
SPICE level analysis of Single Event Effects in an OxRRAM cell. 1-5
Session 8: Design for Testability
- Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
A test time theorem and its applications. 1-5 - Wenceslas Rahajandraibe, Fayrouz Haddad, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal:
Built-in tuning of the local oscillator for open loop modulation of low cost, low power RF transceiver. 1-4
Session 9: Memory Testing and Repair
- Worawit Somha, Hiroyuki Yamauchi:
A RTN variation tolerant guard band design for a deeper nanometer scaled SRAM screening test: Based on EM Gaussians mixtures approximations model of long-tail distributions. 1-6 - Felipe Lavratti, Letícia Maria Veiras Bolzani, Andrea Calimera, Fabian Vargas, Enrico Macii:
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs. 1-6
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