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ORCIDJournal of Electronic Testing, Volume 31
Volume 31, Number 1, February 2015
- Vishwani D. Agrawal:
Editorial. 1-2 - New Editors - 2015. 3-6
- 2014 JETTA Reviewers. 7-8
- Test Technology Newsletter. 9-10
- Shane Kelly
, Xuehui Zhang, Mohammad Tehranipoor, Andrew Ferraiuolo:
Detecting Hardware Trojans using On-chip Sensors in an ASIC Design. 11-26 - Tieqiao Liu, Yingbo Zhou, Yi Liu, Shuo Cai:
Harzard-Based ATPG for Improving Delay Test Quality. 27-34 - Yukun Gao, Tengteng Zhang, Punj Pokharel, Swati Chakraborty, D. M. H. Walker:
Pseudo Functional Path Delay Test through Embedded Memories. 35-42 - Haiying Yuan, Kun Guo, Xun Sun, Jiaping Mei, Hongying Song:
A Power Efficient BIST TPG Method on Don't Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering. 43-52 - Dongsheng Zhao, Yuzhu He:
A New Test Point Selection Method for Analog Circuit. 53-66 - B. M. Farid Rahman, Yujia Peng, TengXing Wang, Tian Xia, Guoan Wang:
On-Wafer Calibration Technique for High Frequency Measurement with Simultaneous Voltage and Current Tuning. 67-73 - Mohamed Metwally, Nicholai L'Esperance, Tian Xia:
Compressive Sampling Coupled OFDM Technique for Testing Continuous Wave Radar. 75-83 - Nicholas Tzou, Debesh Bhatta, Barry J. Muldrey, Thomas Moon, Xian Wang, Hyun Woo Choi, Abhijit Chatterjee:
Low Cost Sparse Multiband Signal Characterization Using Asynchronous Multi-Rate Sampling: Algorithms and Hardware. 85-98 - Tengteng Zhang, Yukun Gao, D. M. H. Walker:
Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. 99-106 - Stefan R. Vock, Omar Escalona, Colin Turner:
Improving Semiconductor Reliability with Advanced Engineering Methods in Test Program Development. 107-117 - Wenxin Yu, Yigang He:
Analog Circuit Fault Diagnosis via Sensitivity Computation. 119-122
Volume 31, Number 2, April 2015
- Vishwani D. Agrawal:
Editorial. 123 - Test Technology Newsletter. 125-126
- Hsun-Cheng Lee, Jacob A. Abraham:
Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction. 127-138 - Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez, Eduardo Chielle, Fernanda Lima Kastensmidt:
Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors. 139-150 - Jörg Behrend, Djones Lettnin, Alexander Grünhage, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
Scalable and Optimized Hybrid Verification of Embedded Software. 151-166 - Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Francesco Stefanni, Tara Ghasempouri, Michele Lora, Giovanni Auditore, Mirella Negro Marcigaglia:
Reusing RTL Assertion Checkers for Verification of SystemC TLM Models. 167-180 - Ryan H.-M. Huang, Dennis K.-H. Hsu, Charles H.-P. Wen:
A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs. 181-192 - Liang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control Paths. 193-206 - Igor Gadelha Pereira, Leonardo Alves Dias, Cleonilson Protásio de Souza:
A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis. 207-215 - Xuan Xie, Xifeng Li, Dongjie Bi, Qizhong Zhou, Sanshan Xie, Yongle Xie:
Analog Circuits Soft Fault Diagnosis Using Rényi's Entropy. 217-224
Volume 31, Number 3, June 2015
- Vishwani D. Agrawal:
Editorial. 225 - Test Technology Newsletter. 227-228
- Abdelghani Renbi, Jerker Delsing:
Contactless Testing of Circuit Interconnects. 229-253 - Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang:
A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models. 255-273 - Marko S. Andjelkovic, Vladimir Petrovic, Zoran Stamenkovic, Goran S. Ristic, Goran S. Jovanovic:
Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch. 275-289 - Li Wang, Lianping Guo, Jun Jiang, Duyu Qiu:
A Hilbert-Transform-Based Method to Estimate and Correct Timing Error in Time-Interleaved ADCs. 291-299 - Farnaz Fotovatikhah, Bahareh Naraghi, Fatemeh Tavakoli, Mahdiar Ghadiry:
A New Approach to Model the Effect of Topology on Testing Using Boundary Scan. 301-310 - Subhamita Mukherjee, Tuhina Samanta:
Distributed Scan Like Fault Detection and Test Optimization for Digital Microfluidic Biochips. 311-319 - Debesh Kumar Das, Hideo Fujiwara:
One More Class of Sequential Circuits having Combinational Test Generation Complexity. 321-327 - Xiaopeng Yu, Rong Qian Tian, Wen Lin Xu, Zheng Shi:
A New On-chip Signal Generator for Charge-Based Capacitance Measurement Circuit. 329-333
Volume 31, Number 4, August 2015
- Vishwani D. Agrawal:
Editorial. 335 - Test Technology Newsletter. 337-338
- Abdelghani Renbi, Jerker Delsing:
Application of Contactless Testing to PCBs with BGAs and Open Sockets. 339-347 - Zhengfeng Huang, Huaguo Liang, Sybille Hellebrand:
A High Performance SEU Tolerant Latch. 349-359 - Alfonso Martínez-Cruz, Ricardo Barrón Fernández, Herón Molina-Lozano, Marco Antonio Ramírez Salinas, Luis Alfonso Villa Vargas:
Automated Functional Test Generation for Digital Systems Through a Compact Binary Differential Evolution Algorithm. 361-380 - Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld:
Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors. 381-394 - Haibin Wang, Rui Liu, Li Chen, Jinshun Bi, Mulong Li, Yuanqing Li:
A Novel Built-in Current Sensor for N-WELL SET Detection. 395-401 - Sindhu Gunasekar, Vishwani D. Agrawal:
A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing. 403-410 - Alexandre Simionovski, Rafael Galhardo Vaz, Odair Lelis Goncalez, Gilson I. Wirth:
Impact of Total Ionizing Dose on Bulk Built-In Current Sensors with Dynamic Storage Cell. 411-417 - Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi:
Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. 419
Volume 31, Numbers 5-6, December 2015
- Vishwani D. Agrawal:
Editorial. 421-422 - Test Technology Newsletter. 423-424
- 2014 JETTA-TTTC Best Paper Award. 425
- Tong-Yu Hsieh, Chih-Hao Wang, Chun-Wei Kuo, Shu-Yu Huang, Tsung-Liang Chih:
Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement. 427-441 - Stephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre:
Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range. 443-459 - Zewen Hu, Mingqing Xiao, Lei Zhang, Haifang Song, Zhao Yang:
Incipient Fault Diagnostics and Remaining Useful Life Prediction of Analog Filters. 461-477 - Suraj Sindia, Vishwani D. Agrawal:
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. 479-489 - Michal Tadeusiewicz, Andrzej Kuczynski, Stanislaw Halgas:
Spot Defect Diagnosis in Analog Nonlinear Circuits with Possible Multiple Operating Points. 491-502 - Nima Aghaee, Zebo Peng, Petru Eles:
A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs. 503-523 - Sezer Gören, Cemil Cem Gürsoy, Abdullah Yildiz:
Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection. 525-536 - Yuanqing Li, Haibin Wang, Suying Yao, Xi Yan, Zhiyuan Gao, Jiangtao Xu:
Double Node Upsets Hardened Latch Circuits. 537-548 - Yu-Yi Chen, Jiun-Lang Huang, Terry Kuo, Xuan-Lun Huang:
Design and Implementation of an FPGA-Based Data/Timing Formatter. 549-559 - Lixiang Li, Yuanqing Li, Haibin Wang, Rui Liu, Qiong Wu, Michael Newton, Yuan Ma, Li Chen:
Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology. 561-568
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