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ORCIDFlorian Zaruba
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- affiliation: Axelera AI, Zürich, Switzerland
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2020 – today
- 2024
[c13]Pascal Alexander Hager, Bert Moons, Stefan Cosemans, Ioannis A. Papistas, Bram Rooseleer, Jeroen Van Loon, Roel Uytterhoeven, Florian Zaruba, Spyridoula Koumousi, Milos Stanisavljevic, Stefan Mach, Sebastiaan Mutsaards, Riduan Khaddam Aljameh, Gua Hao Khov, Brecht Machiels, Cristian Olar, Anastasios Psarras, Sander Geursen, Jeroen Vermeeren, Yi Lu, Abhishek Maringanti, Deepak Ameta, Leonidas Katselas, Noah Hütter, Manuel Schmuck, Swetha Sivadas, Karishma Sharma, Manuel Oliveira, Ramon Aerne, Nitish Sharma, Timir Soni, Beatrice Bussolino, Djordje Pesut, Michele Pallaro, Andrei Podlesnii, Alexios Lyrakis, Yannick Ruffiner, Martino Dazzi, Johannes Thiele, Koen Goetschalckx, Nazareno Bruschi, Jonas Doevenspeck, Bram Verhoef, Stefan Linz, Giuseppe Garcea, Jonathan Ferguson, Ioannis Koltsidas, Evangelos Eleftheriou:
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge. ISSCC 2024: 212-214- 2023
- [j8]Paul Scheffler
, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. IEEE Trans. Parallel Distributed Syst. 34(12): 3147-3161 (2023) - [c12]Gianmarco Ottavi, Florian Zaruba, Luca Benini, Davide Rossi:
Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU. DSD 2023: 429-435 - [i9]Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. CoRR abs/2305.05559 (2023) - 2022
- [j7]Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini:
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. IEEE Trans. Computers 71(8): 1794-1809 (2022) - 2021
- [b1]Florian Zaruba:
Energy-efficient high-performance computing. ETH Zurich, Zürich, Switzerland, Hartung-Gorre Verlag 2021, ISBN 978-3-86628-720-4, pp. 1-209 - [j6]Florian Zaruba, Fabian Schuiki, Luca Benini:
Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing. IEEE Micro 41(2): 36-42 (2021) - [j5]Fabian Schuiki, Florian Zaruba, Torsten Hoefler, Luca Benini:
Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. IEEE Trans. Computers 70(2): 212-227 (2021) - [j4]Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads. IEEE Trans. Computers 70(11): 1845-1860 (2021) - [j3]Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini:
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 774-787 (2021) - [c11]Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. DATE 2021: 1787-1792 - [c10]Thomas Benz, Luca Bertaccini, Florian Zaruba, Fabian Schuiki, Frank K. Gürkaynak, Luca Benini:
A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range. ESSCIRC 2021: 263-266 - [c9]Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini:
Banshee: A Fast LLVM-Based RISC-V Binary Translator. ICCAD 2021: 1-9 - [c8]Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini:
Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. ISCAS 2021: 1-5 - 2020
- [j2]Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini:
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 530-543 (2020) - [c7]Jonathan Balkind, Katie Lim, Michael Schaffner, Fei Gao, Grigory Chirkov, Ang Li, Alexey Lavrov, Tri M. Nguyen, Yaosheng Fu, Florian Zaruba, Kunal Gulati, Luca Benini, David Wentzlaff:
BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research. ASPLOS 2020: 699-714 - [c6]Andreas Kurth, Samuel Riedel, Florian Zaruba, Torsten Hoefler, Luca Benini:
ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor. DAC 2020: 1-6 - [c5]Florian Zaruba, Fabian Schuiki, Luca Benini:
A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. Hot Chips Symposium 2020: 1-24 - [c4]Alfio Di Mauro, Florian Zaruba, Fabian Schuiki, Stefan Mach, Luca Benini:
Live Demonstration: Exploiting Body-Biasing for Static Corner Trimming and Maximum Energy Efficiency Operation in 22nm FDX Technology. ISCAS 2020: 1 - [i8]Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads. CoRR abs/2002.10143 (2020) - [i7]Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini:
FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing. CoRR abs/2007.01530 (2020) - [i6]Florian Zaruba, Fabian Schuiki, Luca Benini:
Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. CoRR abs/2008.06502 (2020) - [i5]Andreas Kurth, Wolfgang Rönninger, Thomas Benz, Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Luca Benini:
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. CoRR abs/2009.05334 (2020) - [i4]Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. CoRR abs/2011.08070 (2020)
2010 – 2019
- 2019
- [j1]Florian Zaruba, Luca Benini:
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2629-2640 (2019) - [c3]Florian Zaruba, Fabian Schuiki, Stefan Mach, Luca Benini:
The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and Performance. ICECS 2019: 767-770 - [c2]Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini:
A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI. VLSI-SoC 2019: 95-98 - [i3]Florian Zaruba, Luca Benini:
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology. CoRR abs/1904.05442 (2019) - [i2]Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini:
Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI. CoRR abs/1906.00478 (2019) - [i1]Fabian Schuiki, Florian Zaruba, Torsten Hoefler, Luca Benini:
Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. CoRR abs/1911.08356 (2019) - 2018
- [c1]Pasquale Davide Schiavone, Ernesto Sánchez, Annachiara Ruospo, Francesco Minervini, Florian Zaruba, Germain Haugou, Luca Benini:
An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study. VLSI-SoC 2018: 43-48
Coauthor Index
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