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ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 26
Volume 26, Number 1, January 2021
- Abhinav Goel, Sarah Aghajanzadeh, Caleb Tung, Shuo-Han Chen
, George K. Thiruvathukal, Yung-Hsiang Lu:
Modular Neural Networks for Low-Power Image Classification on Embedded Devices. 1:1-1:35 - Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia:
FaultDroid: An Algorithmic Approach for Fault-Induced Information Leakage Analysis. 2:1-2:27 - Jun Li, Bowen Huang, Zhibing Sha, Zhigang Cai, Jianwei Liao, Balazs Gerofi, Yutaka Ishikawa:
Mitigating Negative Impacts of Read Disturb in SSDs. 3:1-3:24 - Ankit Mondal, Ankur Srivastava:
Ising-FPGA: A Spintronics-based Reconfigurable Ising Model Solver. 4:1-4:27 - Seyed Ali Rokni, Marjan Nourollahi, Parastoo Alinia, Seyed-Iman Mirzadeh, Mahdi Pedram, Hassan Ghasemzadeh:
TransNet: Minimally Supervised Deep Transfer Learning for Dynamic Adaptation of Wearable Systems. 5:1-5:31 - Sheikh Ariful Islam, Love Kumar Sah, Srinivas Katkoori:
High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging. 6:1-6:35 - Sudip Poddar, Tapalina Banerjee, Robert Wille, Bhargab B. Bhattacharya:
Robust Multi-Target Sample Preparation on MEDA Biochips Obviating Waste Production. 7:1-7:29 - Ying Zhang, Xinpeng Hong, Zhongsheng Chen, Zebo Peng, Jianhui Jiang:
A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip. 8:1-8:26
Volume 26, Number 2, February 2021
- Stephano Machado Moreira Goncalves, Leomar S. da Rosa Jr., Felipe S. Marques:
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling. 9:1-9:38 - Tuotian Liao, Lihong Zhang:
Efficient Parasitic-aware gm/ID-based Hybrid Sizing Methodology for Analog and RF Integrated Circuits. 10:1-10:31 - Nan Wu, Lei Deng, Guoqi Li, Yuan Xie:
Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning. 11:1-11:27 - Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda:
Leakage-Aware Dynamic Thermal Management of 3D Memories. 12:1-12:31 - Sumana Ghosh, Soumyajit Dey, Pallab Dasgupta:
Performance-Driven Post-Processing of Control Loop Execution Schedules. 13:1-13:27 - Yingyi Luo, Joshua C. Zhao, Arnav Aggarwal, Seda Ogrenci-Memik, Kazutomo Yoshii:
Thermal Management for FPGA Nodes in HPC Systems. 14:1-14:17 - Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang:
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization. 15:1-15:28 - Aqeeb Iqbal Arka, Biresh Kumar Joardar, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande:
HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration. 16:1-16:21
Volume 26, Number 3, February 2021
- Dipika Deb, John Jose, Maurizio Palesi:
COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC-based MPSoCs. 17:1-17:31 - Martín Letras, Joachim Falk, Tobias Schwarzer, Jürgen Teich:
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements. 18:1-18:33 - Irith Pomeranz, M. Enamul Amyeen:
Logic Diagnosis with Hybrid Fail Data. 19:1-19:13 - Mehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev:
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops. 20:1-20:18 - Anteneh Gebregiorgis, Mehdi B. Tahoori:
Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic Systems. 21:1-21:23 - Yangdi Lyu, Prabhat Mishra:
MaxSense: Side-channel Sensitivity Maximization for Trojan Detection Using Statistical Test Patterns. 22:1-22:21 - Irith Pomeranz:
Covering Test Holes of Functional Broadside Tests. 23:1-23:15 - Urmimala Roy, Tanmoy Pramanik, Subhendu Roy, Avhishek Chatterjee, Leonard F. Register, Sanjay Kumar Banerjee:
Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory. 24:1-24:17
Volume 26, Number 4, April 2021
- Irith Pomeranz:
Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors. 25:1-25:15 - Hasini Witharana, Yangdi Lyu, Prabhat Mishra:
Directed Test Generation for Activation of Security Assertions in RTL Models. 26:1-26:28 - Naser Mohammadzadeh, Robert Wille, Oliver Keszöcze:
Efficient One-pass Synthesis for Digital Microfluidic Biochips. 27:1-27:21 - Ayush Jain, Ziqi Zhou, Ujjwal Guin:
TAAL: Tampering Attack on Any Key-based Logic Locked Circuits. 28:1-28:22 - M. Sazadur Rahman, Adib Nahiyan, Fahim Rahman, Saverio Fazzari, Kenneth Plaks, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor:
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks. 29:1-29:27 - Mitali Sinha, Sri Harsha Gade, Pramit Bhattacharyya, Sujay Deb:
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems. 30:1-30:31 - Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar:
Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion. 31:1-31:34
- Pruthvy Yellu, Landon Buell, Miguel Mark, Michel A. Kinsy, Dongpeng Xu, Qiaoyan Yu:
Security Threat Analyses and Attack Models for Approximate Computing Systems: From Hardware and Micro-architecture Perspectives. 32:1-32:31
Volume 26, Number 5, June 2021
- Darshana Jayasinghe, Aleksandar Ignjatovic, Roshan G. Ragel, Jude Angelo Ambrose, Sri Parameswaran:
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks. 33:1-33:36 - Chin-Hsien Wu, Hao-Wei Zhang, Chia-Wei Liu, Ta-Ching Yu, Chi-Yen Yang:
A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory. 34:1-34:25 - Eunjin Jeong, Dowhan Jeong, Soonhoi Ha:
Dataflow Model-based Software Synthesis Framework for Parallel and Distributed Embedded Systems. 35:1-35:38 - Guoqi Xie, Hao Peng, Xiongren Xiao, Yao Liu, Renfa Li:
Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded Devices. 36:1-36:18 - Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim:
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements. 37:1-37:25 - Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen:
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis. 38:1-38:22 - Lang Feng, Jeff Huang, Jiang Hu, Abhijith Reddy:
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation. 39:1-39:39
- Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, Xuefei Ning, Yuzhe Ma, Haoyu Yang, Bei Yu, Huazhong Yang, Yu Wang:
Machine Learning for Electronic Design Automation: A Survey. 40:1-40:46
Volume 26, Number 6, November 2021
- Saranyu Chattopadhyay, Pranesh Santikellur, Rajat Subhra Chakraborty, Jimson Mathew, Marco Ottavi:
A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability. 41:1-41:24 - Chen Jiang, Bo Yuan, Tsung-Yi Ho, Xin Yao:
Placement of Digital Microfluidic Biochips via a New Evolutionary Algorithm. 42:1-42:22 - Dennis R. E. Gnad, Cong Dang Khoa Nguyen, Syed Hashim Gillani, Mehdi B. Tahoori:
Voltage-Based Covert Channels Using FPGAs. 43:1-43:25 - Xuefei Ning, Guangjun Ge, Wenshuo Li, Zhenhua Zhu, Yin Zheng, Xiaoming Chen, Zhen Gao, Yu Wang, Huazhong Yang:
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture. 44:1-44:24 - Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu:
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference. 45:1-45:18 - Pushpita Roy, Ansuman Banerjee:
A Framework for Validation of Synthesized MicroElectrode Dot Array Actuations for Digital Microfluidic Biochips. 46:1-46:36 - Xi Li, Soheil Nazar Shahsavani, Xuan Zhou, Massoud Pedram, Peter A. Beerel:
A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits. 47:1-47:17 - Naebeom Park, Sungju Ryu, Jaeha Kung, Jae-Joon Kim:
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory. 48:1-48:20 - Mohammad Ali Maleki, Alireza Nabipour-Meybodi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
An Energy-Efficient Inference Method in Convolutional Neural Networks Based on Dynamic Adjustment of the Pruning Level. 49:1-49:20 - Dave Y.-W. Lin, Charles H.-P. Wen:
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability. 50:1-50:12
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